Abstract
This paper describes our results of the AMNS modular multiplication algorithm for efficient implementations of ECC over \(\mathbb {F}_p\) on the Hardware/Software (HW/SW) implementation in FPGA. We provide both arithmetic operators and computation architectures optimized for high speed. We also compare our results with the implementation of the CIOS method for modular multiplication.
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Chaouch, A., Dosso, Y.F., Didier, LS., El Mrabet, N., Ouni, B., Bouallegue, B. (2020). Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation. In: Kallel, S., Cuppens, F., Cuppens-Boulahia, N., Hadj Kacem, A. (eds) Risks and Security of Internet and Systems. CRiSIS 2019. Lecture Notes in Computer Science(), vol 12026. Springer, Cham. https://doi.org/10.1007/978-3-030-41568-6_8
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DOI: https://doi.org/10.1007/978-3-030-41568-6_8
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