Tests and Results



The new analog IC yield estimation methodology was implemented in the state-of-the-art AIDA-C analog IC sizing and optimization tool aiming to offer a new MC-based yield optimization process. The new yield optimization feature of AIDA-C must have a reduced time impact in the overall optimization processes and yield estimation accuracy according to IC designers’ requirements. Since the new yield estimation methodology is based on clustering techniques, several clustering algorithms were tested, and the respective results were compared to assess which clustering algorithm provides the best results in terms of execution time and accuracy. This chapter also details a comparison of memory requirements for running each clustering algorithm in the new yield estimation methodology. The number of clusters reduction technique previously described, and adopted in the FUZYE methodology, is validated using cluster validity indexes.


Monte Carlo analysis Analog IC yield estimation Clustering algorithms 


  1. 1.
    R. Povoa, N. Lourenco, N. Horta, R. Santos-Tavares, J. Goes, Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners, in 2013 IFIP/IEEE 21st Int. Conf. Very Large Scale Integration (VLSI-SoC), 2013Google Scholar
  2. 2.
    M. Pandey, A. Canelas, R. Póvoa, J.A. Torres, J.C. Freire, N. Lourenço, N. Horta, Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. Integration VLSI J 55, 330–340 (2016)CrossRefGoogle Scholar
  3. 3.
    A. Canelas, R. Póvoa, R. Martins, N. Lourenço, J. Guilherme, N. Horta, A 20 DB gain two-stage low-noise amplifier with high yield for 5 GHz applications, in 15th Int. Conf. Synthesis, Modeling, Anal. Simulation Methods Appl. Circuit Des. (SMACD), Prague, Czech Republic, 2018Google Scholar
  4. 4.
    A. Canelas, R. Martins, R. Póvoa, N. Lourenço, N. Horta, Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations, in 13th Int. Conf. Synthesis, Modeling, Anal. Simulation Methods Appl. Circuit Des. (SMACD), Lisbon, 2016Google Scholar
  5. 5.
    R. Spence, R. Soin, Tolerance Design of Electronic Circuits (Addison-Wesley, Wokingham, 1988)Google Scholar
  6. 6.
    M. Meehan, J. Purviance, Yield and Reliability Design for Microwave Circuits and Systems (Artech House, Norwood, MA, 1993)Google Scholar
  7. 7.
    K.Y. Mitra, E. Sowade, C. Martínez-Domingo, E. Ramon, J. Carrabina, H.L. Gomes, R.R. Baumann, Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics, in Proc. AIP Conf., 2015Google Scholar
  8. 8.
    Fujifilm Dimatix, Materials Printer & Cartridge DMP-2800 Series Printer & DMC-11600 Series Cartridge FAQ Report, 21 Apr 2016Google Scholar
  9. 9.
    A. Canelas, R. Martins, R. Póvoa, N. Lourenço, N. Horta, Efficient Yield Optimization Method Using a Variable K-means Algorithm for Analog IC Sizing, in 2017 Des. Automat. Test Eur. Conf. Exhibition (DATE), Lausanne, 2017Google Scholar
  10. 10.
    M. Pak, F.V. Fernandez, G. Dundar, Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis. Integration VLSI J. 55, 357–365 (2016)CrossRefGoogle Scholar
  11. 11.
    E. Afacan, G. Berkol, G. Dundar, A.E. Pusane, F. Baskaya, An analog circuit synthesis tool based on efficient and reliable yield estimation. Microelectron. J. 54, 14–22 (2016)CrossRefGoogle Scholar

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© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Instituto Superior TécnicoInstituto de TelecomunicaçõesLisbonPortugal
  2. 2.Instituto Politécnico de TomarInstituto de TelecomunicaçõesLisbonPortugal

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