Abstract
The new analog IC yield estimation methodology was implemented in the state-of-the-art AIDA-C analog IC sizing and optimization tool aiming to offer a new MC-based yield optimization process. The new yield optimization feature of AIDA-C must have a reduced time impact in the overall optimization processes and yield estimation accuracy according to IC designers’ requirements. Since the new yield estimation methodology is based on clustering techniques, several clustering algorithms were tested, and the respective results were compared to assess which clustering algorithm provides the best results in terms of execution time and accuracy. This chapter also details a comparison of memory requirements for running each clustering algorithm in the new yield estimation methodology. The number of clusters reduction technique previously described, and adopted in the FUZYE methodology, is validated using cluster validity indexes.
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Canelas, A.M.L., Guilherme, J.M.C., Horta, N.C.G. (2020). Tests and Results. In: Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies. Springer, Cham. https://doi.org/10.1007/978-3-030-41536-5_6
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DOI: https://doi.org/10.1007/978-3-030-41536-5_6
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