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Yield Estimation Techniques Related Work

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Abstract

The aggressive shrinking of devices, brought by new CMOS technology nodes, makes that any small process variations induce a larger impact on circuit devices behavior. Transistors having less than one hundred atoms per channel region or any minor variation in the dopant implantation may lead to increasing mismatch problems (Wirnshofer, Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits, Springer, Dordrecht, 2013). Therefore, variability analysis has a critical role in order to predict the undesirable effects caused by process variations. Different techniques have been proposed to estimate the impact of variations in circuit performances at early stages of the analog design flow. In this chapter, the most relevant techniques in yield estimation are detailed. Also, several automatic analog IC sizing techniques considering variability effects are discussed. At the end of this chapter, the yield estimation and variation-aware techniques adopted by commercial EDA tools are presented.

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Authors and Affiliations

  1. Instituto Superior Técnico, Instituto de Telecomunicações, Lisbon, Portugal

    António Manuel Lourenço Canelas & Nuno Cavaco Gomes Horta

  2. Instituto Politécnico de Tomar, Instituto de Telecomunicações, Lisbon, Portugal

    Jorge Manuel Correia Guilherme

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  1. António Manuel Lourenço Canelas
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  3. Nuno Cavaco Gomes Horta
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Canelas, A.M.L., Guilherme, J.M.C., Horta, N.C.G. (2020). Yield Estimation Techniques Related Work. In: Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies. Springer, Cham. https://doi.org/10.1007/978-3-030-41536-5_3

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  • DOI: https://doi.org/10.1007/978-3-030-41536-5_3

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  • Online ISBN: 978-3-030-41536-5

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