Analog IC Sizing Background



Analog designers often have to compromise on some circuit performances to achieve a handmade solution, due to the large number of constraints that must be fulfilled. This fact led to the appearance of several techniques and tools for the automation of analog IC sizing by both academy and industry. Despite the evolution of those techniques and tools, a substantial part of analog sizing tasks is still dependent on human intervention. Paradoxically, experience shows that once an EDA sizing tool finds a solution, a designer is able to improve that solution by adjusting one or a very small number of design parameters, and the paradox is that the designer was unable to achieve that original EDA optimal solution by himself, mainly due to the large number of constraints that must be satisfied. To understand how today’s EDA tools reach solutions and how a yield estimation technique can be embedded in those tools, this chapter presents information about the different techniques adopted in automatic analog IC sizing tools. Additionally, some background information about circuit parameters considered during the sizing process is also provided.


Automatic analog IC sizing Circuit design parameters Circuit performance parameters Feasibility space Parametric yield 


  1. 1.
    F. Medeiro, R. Rodríguez-Macías, F. Fernández, R. Domínguez-Castro, J. Huertas, A. Rodríguez-Vázquez, Global design of analog cells using statistical optimization techniques. Analog Integr. Circ. Sig. Process 6(3), 179–195 (1994)CrossRefGoogle Scholar
  2. 2.
    E. Nowak, I. Aller, T. Ludwig, K. Kim, R. Joshi, C.-T. Chuang, K. Bernstein, R. Puri, Turning silicon on its edge [double gate CMOS/FinFET technology]. IEEE Circuits Devices Mag. 20(1), 20–31 (2004)CrossRefGoogle Scholar
  3. 3.
    B. Swahn, S. Hassoun, Gate sizing: finFETs vs 32nm bulk MOSFETs, in 2006 43rd ACM/IEEE Des. Automat. Conf., San Francisco, CA, 2006Google Scholar
  4. 4.
    R.A. Rutenbar, Analog layout synthesis: what’s missing? in Proc. 19th Int. Symp. Physical Des., San Francisco, CA, USA, 2010Google Scholar
  5. 5.
    B. Dobkin, J. Williams, Analog Circuit Design, Immersion in the Black Art of Analog Design, vol 2 (Newnes, Amsterdam, 2013)Google Scholar
  6. 6.
    R. Lourenço, N. Lourenço, N. Horta, AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing (Springer International Publishing, Cham, 2015)zbMATHCrossRefGoogle Scholar
  7. 7.
    G.G.E. Gielen, R.A. Rutenbar, Computer-aided design of analog and mixed-signal integrated circuits. Proc. IEEE 88(12), 1825–1854 (2000)CrossRefGoogle Scholar
  8. 8.
    A. Gerlach, J. Scheible, T. Rosahl, F. Eitrich, A generic topology selection method for analog circuits demonstrated on the OTA example, in 2015 11th Conf. Ph.D. Research in Microelectronics and Electronics (PRIME), Glasgow, 2015Google Scholar
  9. 9.
    P. Veselinovic, D. Leenaerts, W. van Bokhoven, F. Leyn, F. Proesmans, G. Gielen, W. Sansen, A flexible topology selection program as part of an analog synthesis system, in Proc. 1995 European Conf. Design and Test, Washington, DC, USA, 1995Google Scholar
  10. 10.
    A. Gerlach, T. Rosahl, F.-T. Eitrich, J. Scheible, A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA example, in 2017 Des. Automat. Test Eur. Conf. Exhibition (DATE), Lausanne, Switzerland, 2017Google Scholar
  11. 11.
    H.E. Graeb, Analog Design Centering and Sizing (Springer, Dordrecht, 2007)Google Scholar
  12. 12.
    N. Lourenço, R. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects (Springer International Publishing, Cham, 2017)CrossRefGoogle Scholar
  13. 13.
    R. Schwencker, F. Schenkel, M. Pronath, H. Graeb, Analog circuit sizing using adaptive worst-case parameter sets, in 2002 Des. Automat. Test Eur. Conf. Exhibition (DATE), Paris, France, 2002Google Scholar
  14. 14.
    R. Martins, N. Lourenço, A. Canelas, N. Horta, Stochastic-based placement template generator for analog IC layout-aware synthesis. Integration VLSI J. 58, 485–495 (2017)CrossRefGoogle Scholar
  15. 15.
    R. Martins, N. Lourenço, N. Horta, Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques (Springer International Publishing, Cham, 2017)Google Scholar
  16. 16.
    B. Cardoso, R. Martins, N. Lourenço, N. Horta, AIDA-PEx: accurate parasitic extraction for layout-aware analog integrated circuit sizing, in 2015 11th Conf. Ph.D. Res. Microelectron. Electron. (PRIME), Glasgow, 2015Google Scholar
  17. 17.
    Tanner Calibre One Suite, Mentor Graphics, a Siemens Business. [Online]. Available: Accessed 12 Nov 2018
  18. 18.
    M. Barros, J. Guilherme, N. Horta, Analog Circuits and Systems Optimization Based on Evolutionary Computation Techniques (Springer-Verlag, Berlin, 2010)zbMATHCrossRefGoogle Scholar
  19. 19.
    M. Degrauwe, O. Nys, E. Dijkstra, et al., IDAC: an interactive design tool for analog CMOS circuits. IEEE J. Solid-State Circuits 22(6), 1106–1116 (1987)CrossRefGoogle Scholar
  20. 20.
    R. Harjani, R. Rutenbar, L. Carley, OASYS: a framework for analog circuit synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), 1247–1266 (1989)CrossRefGoogle Scholar
  21. 21.
    N. Horta, J.E. Franca, High-level data conversion synthesis by symbolic methods, in IEEE Int. Symp. on Circuits and Systems. ISCAS 96, Atlanta, GA, 1996Google Scholar
  22. 22.
    N. Horta, J.E. Franca, Algorithm-driven synthesis of data conversion architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), 1116–1135 (1997)CrossRefGoogle Scholar
  23. 23.
    N. Horta, Analogue and mixed-signal systems topologies exploration using symbolic methods. Analog Integr. Circuits Sig. Process. 31(2), 161–176 (2002)CrossRefGoogle Scholar
  24. 24.
    D. Stefanovic, M. Kayal, M. Pastre, V.B. Litovski, Procedural analog design (PAD) tool, in Proc. 4th Int. Symp. on Quality Electronic Design, 2003Google Scholar
  25. 25.
    D. Stefanovic, M. Kayal, Structured Analog CMOS Design, 1st edn. (Springer, Dordrecht, 2008)CrossRefGoogle Scholar
  26. 26.
    F. El-Turky, E.E. Perry, BLADES: an artificial intelligence approach to analog circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6), 680–692 (1989)CrossRefGoogle Scholar
  27. 27.
    C. Toumazou, C.A. Makris, Analog IC design automation. I. Automated circuit generation: new concepts and methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), 218–238 (1995)CrossRefGoogle Scholar
  28. 28.
    C.A. Makris, C. Toumazou, Analog IC design automation. II. Automated circuit correction by qualitative reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), 239–254 (1995)CrossRefGoogle Scholar
  29. 29.
    C. Faragó, A. Lodin, R. Groza, An operational transcondutance amplifier sizing methodology with genetic algorithm-based optimization. Acta Technica Napocensis. Electronica-Telecomunicatii 55(1), 15–20 (2014)Google Scholar
  30. 30.
    Cadence Design Systems, Inc., Virtuoso analog design environment family, 2014. [Online]. Available: Accessed 13 Sept 2018
  31. 31.
    MunEDA GmbH,—Solutions optimization overview, 2018. [Online]. Available: Accessed 13 Sept 2018
  32. 32.
    D. Payne,—Analog circuit optimization, 18 Apr 2012. [Online]. Available: Accessed 13 Sept 2018
  33. 33.
    Synopsys, Inc., Synopsys completes acquisition of magma design automation, 22 Feb 2012. [Online]. Available: Accessed 13 Sept 2018
  34. 34.
    H. Graeb, S. Zizala, J. Eckmueller, K. Antreich, The sizing rules method for analog integrated circuit design, in IEEE/ACM Int. Conf. Comput. Aided Des. ICCAD 2001, San Jose, CA, USA, 2001Google Scholar
  35. 35.
    T. Massier, H. Graeb, U. Schlichtmann, The sizing rules method for CMOS and bipolar analog integrated circuit synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), 2209–2222 (2008)CrossRefGoogle Scholar
  36. 36.
    S. Kiranyaz, T. Ince, M. Gabbouj, Optimization techniques: an overview, in Multidimensional Particle Swarm Optimization for Machine Learning and Pattern Recognition, (Springer, Berlin, 2014), pp. 13–44zbMATHCrossRefGoogle Scholar
  37. 37.
    E. Tas, M. Memmedli, Near optimal step size and momentum in gradient descent for quadratic functions. Turk. J. Math. 41(1), 110–121 (2017)MathSciNetzbMATHCrossRefGoogle Scholar
  38. 38.
    G.K. Wen, M. Mamat, I.B. Mohd, Y. Dasril, A novel of step size selection procedures for steepest descent method. Appl. Math. Sci. 6(51), 2507–2518 (2012)MathSciNetzbMATHGoogle Scholar
  39. 39.
    T.C. Hu, A.B. Kahng, Linear and Integer Programming Made Easy (Springer International Publishing, Cham, 2016)zbMATHCrossRefGoogle Scholar
  40. 40.
    W.L. Winston, Operations Research: Applications and Algorithms, 4th edn. (Brooks/Cole—Thomson Learning, Belmont, CA, 2004)zbMATHGoogle Scholar
  41. 41.
    S. Boyd, S.-J. Kim, L. Vandenberghe, A. Hassibi, A tutorial on geometric programming. J. Optim. Eng. 8(1), 67–127 (2007)MathSciNetzbMATHCrossRefGoogle Scholar
  42. 42.
    S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi, Optimization by simulated annealing. Science 220(4598), 671–680 (1983)MathSciNetzbMATHCrossRefGoogle Scholar
  43. 43.
    Y. Nourani, B. Andresen, A comparison of simulated annealing cooling strategies. J. Phys. A Math. Gen. 31(41), 8373–8385 (1998)zbMATHCrossRefGoogle Scholar
  44. 44.
    V. Torczon, On the convergence of pattern search algorithms. SIAM J. Optim. 7(1), 1–25 (1997)MathSciNetzbMATHCrossRefGoogle Scholar
  45. 45.
    R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, J.R. Hellums, Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6), 703–717 (2000)CrossRefGoogle Scholar
  46. 46.
    J. Kennedy, R. Eberhart, Particle swarm optimization, in Proc. ICNN’95—Int. Conf. Neural Networks, Perth, WA, Australia, 1995Google Scholar
  47. 47.
    M. Juneja, S.K. Nagar, Particle swarm optimization algorithm and its parameters: a review, in 2016 Int. Conf. Contr., Comput., Commun. Mater. (ICCCCM), Allahabad, 2016Google Scholar
  48. 48.
    M. Dorigo, M. Birattari, T. Stutzle, Ant colony optimization. IEEE Comput. Intell. Mag. 1(4), 28–39 (2006)CrossRefGoogle Scholar
  49. 49.
    S.-C. Chu, H.-C. Huang, J.F. Roddick, J.-S. Pan, Overview of algorithms for swarm intelligence, in Comput. Collective Intell. Technol. Appl.: 3rd Int. Conf., ICCCI 2011, Gdynia, Poland, 21–23 Sept 2011, Proc., Part I, ed. by P. Jędrzejowicz, N.T. Nguyen, K. Hoang (2011)Google Scholar
  50. 50.
    C. Blum, Ant colony optimization: introduction and recent trends. Phys. Life Rev. 2(4), 353–373 (2005)CrossRefGoogle Scholar
  51. 51.
    E. Rashedi, H. Nezamabadi-Pour, S. Saryazdi, GSA: a gravitational search algorithm. Inf. Sci. 179(13), 2232–2248 (2009)zbMATHCrossRefGoogle Scholar
  52. 52.
    J.H. Holland, Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control and Artificial Intelligence (MIT Press, Cambridge, MA, 1992)CrossRefGoogle Scholar
  53. 53.
    K. Jebari, M. Madiafi, Selection methods for genetic algorithms. Int. J. Emerg. Sci. 3(4), 333–344 (2013)Google Scholar
  54. 54.
    K. Deb, A. Pratap, S. Agarwal, T. Meyarivan, A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans. Evol. Comput. 6(2), 182–197 (2002)CrossRefGoogle Scholar
  55. 55.
    M. Reyes-sierra, C.A.C. Coello, Multi-objective particle swarm optimizers: a survey of the state-of-the-art. Int. J. Comput. Intell. Res. 2(3), 287–308 (2006)MathSciNetGoogle Scholar
  56. 56.
    Q. Zhang, H. Li, MOEA/D: a multiobjective evolutionary algorithm based on decomposition. IEEE Trans. Evol. Comput. 11(6), 712–731 (2007)CrossRefGoogle Scholar
  57. 57.
    K. Deb, H. Jain, An evolutionary many-objective optimization algorithm using reference-point-based nondominated sorting approach, part I: solving problems with box constraints. IEEE Trans. Evol. Comput. 18(4), 577–601 (2014)CrossRefGoogle Scholar
  58. 58.
    S. Chand, M. Wagner, Evolutionary many-objective optimization: a quick-start guide. Surv. Oper. Res. Manag. Sci. 20(2), 35–42 (2015)MathSciNetGoogle Scholar
  59. 59.
    D.K. Saxena, T. Ray, K. Deb, A. Tiwari, Constrained many-objective optimization: a way forward, in 2009 IEEE Congr. Evol. Computation, Trondheim, 2009Google Scholar
  60. 60.
    H.Y. Koh, C.H. Sequin, P.R. Gray, OPASYN: a compiler for CMOS operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2), 113–125 (1990)CrossRefGoogle Scholar
  61. 61.
    J.P. Harvey, M.I. Elmasry, B. Leung, STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11), 1402–1417 (1992)CrossRefGoogle Scholar
  62. 62.
    Y.L. Chen, W.R. Wu, C.N.J. Liu, J.C.M. Li, Simultaneous optimization of analog circuits with reliability and variability for applications on flexible electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1), 24–35 (2014)CrossRefGoogle Scholar
  63. 63.
    M. del Mar Hershenson, S.P. Boyd, T.H. Lee, Optimal design of a CMOS op-amp via geometric programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), 1–21 (2001)CrossRefGoogle Scholar
  64. 64.
    P. Mandal, V. Visvanathan, CMOS op-amp sizing using a geometric programming formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), 22–38 (2001)CrossRefGoogle Scholar
  65. 65.
    M. del Mar Hershenson, Design of pipeline analog-to-digital converters via geometric programming, in IEEE/ACM Int. Conf. Comput. Aided Des., 2002Google Scholar
  66. 66.
    M. del Mar Hershenson, CMOS analog circuit design via geometric programming, in Proc. Amer. Control Conf., Boston, MA, 2004Google Scholar
  67. 67.
    A.K. Singh, K. Ragab, M. Lok, C. Caramanis, M. Orshansky, Predictable equation-based analog optimization based on explicit capture of modeling error statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10), 1485–1498 (2012)CrossRefGoogle Scholar
  68. 68.
    E.S. Ochotta, R.A. Rutenbar, L.R. Carley, Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3), 273–294 (1996)CrossRefGoogle Scholar
  69. 69.
    L.T. Pileggi, R.A. Rohrer, Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9, 352–366 (1990)CrossRefGoogle Scholar
  70. 70.
    K.H. Meng, P.C. Pan, H.M. Chen, Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping, in 12th Int. Symp. Quality Electron. Des., Santa Clara, CA, 2011Google Scholar
  71. 71.
    B. Benhala, An improved ACO algorithm for the analog circuits design optimization. Int. J. Circuits Syst. Sig. Process. 10, 126–133 (2016)Google Scholar
  72. 72.
    M. Fakhfakh, Y. Cooren, A. Sallem, M. Loulou, P. Siarry, Analog circuit design optimization through the particle swarm optimization technique. Analog Integr. Circuits Sig. Process. 63(1), 71–82 (2010)CrossRefGoogle Scholar
  73. 73.
    S. Kamisetty, J. Garg, J.N. Tripathi, J. Mukherjee, Optimization of analog RF circuit parameters using randomness in particle swarm optimization, in 2011 World Congr. Inform. Commun. Technol., Mumbai, 2011Google Scholar
  74. 74.
    A. El Dor, M. Fakhfakh, P. Siarry, Multiobjective differential evolution algorithm using crowding distance for the optimal design of analog circuits. J. Electr. Syst. 12(3), 612–622 (2016)Google Scholar
  75. 75.
    N. Lourenço, R. Martins, A. Canelas, R. Póvoa, N. Horta, AIDA: layout-aware analog circuit-level sizing with in-loop layout generation. Integration VLSI J. 55, 316–329 (2016)CrossRefGoogle Scholar
  76. 76.
    R. Santos-Tavares, N. Paulino, J. Higino, J. Goes, J.P. Oliveira, Optimization of multi-stage amplifiers in deep-submicron CMOS using a distributed/parallel genetic algorithm, in IEEE Int. Symp. Circuits Syst., Seattle, WA, 2008Google Scholar
  77. 77.
    M. Krasnicki, R. Phelps, R.A. Rutenbar, L.R. Carley, MAELSTROM: efficient simulation-based synthesis for custom analog cells, in Proc. 1999 Des. Autom. Conf., New Orleans, LA, 1999Google Scholar
  78. 78.
    H. Gupta, B. Ghosh, Analog circuits design using ant colony optimization. Int. J. Electron. Comput. Commun. Technol. 2(3), 9–21 (2012)Google Scholar
  79. 79.
    B. Benhala, O. Bouattane, GA and ACO techniques for the analog circuits design optimization. J. Theor. Appl. Inf. Technol. 64(2), 413–419 (2014)Google Scholar
  80. 80.
    M. Dehbashian, M. Maymandi-Nejad, A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique. Integration VLSI J. 56, 148–166 (2017)CrossRefGoogle Scholar
  81. 81.
    M.B. Yelten, T. Zhu, S. Koziel, P.D. Franzon, M.B. Steer, Demystifying surrogate modeling for circuits and systems. IEEE Circuits Syst. Mag. 12(1), 45–63 (2012)CrossRefGoogle Scholar
  82. 82.
    B. Liu, G. Gielen, F.V. Fernández, Automated Design of Analog and High-Frequency Circuits (Springer, Berlin, 2014)zbMATHCrossRefGoogle Scholar
  83. 83.
    R. Bellman, Adaptive Control Processes: A Guided Tour (Princeton University Press, Princeton, NJ, 1961)zbMATHCrossRefGoogle Scholar
  84. 84.
    H. Abdi, L.J. Williams, Principal component analysis. WIREs Comput. Stat. 2(4), 433–459 (2010)CrossRefGoogle Scholar
  85. 85.
    A. Giunta, S. Wojtkiewicz, M. Eldred, Overview of modern design of experiments methods for computational simulations, in 41st Aerospace Sci. Meeting Exhibit, Reno, Nevada, 2003Google Scholar
  86. 86.
    H. Niederreiter, Random number generation and quasi-Monte Carlo methods. Soc. Ind. Appl. Math. (1992)Google Scholar
  87. 87.
    X. Wang, I.H. Sloan, Low discrepancy sequences in high dimensions: how well are their projections distributed? J. Comput. Appl. Math. 213(2), 366–386 (2008)MathSciNetzbMATHCrossRefGoogle Scholar
  88. 88.
    C. Schlier, On scrambled Halton sequences. Appl. Numer. Math. 58(10), 1467–1478 (2008)MathSciNetzbMATHCrossRefGoogle Scholar
  89. 89.
    H. You, M. Yang, D. Wang, X. Jia, Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance, in 2009 10th Int. Symp. Quality Electron. Des., San Jose, CA, 2009Google Scholar
  90. 90.
    G. Matheron, Principles of geostatistics. Econ. Geol. 58(8), 1246–1266 (1963)CrossRefGoogle Scholar
  91. 91.
    F. Yengui, L. Labrak, P. Russo, F. Frantz, N. Abouchi, Optimization based on surrogate modeling for analog integrated circuits, in 2012 19th IEEE Int. Conf. Electron. Circuits Syst. (ICECS 2012), Seville, 2012Google Scholar
  92. 92.
    M. Buhmann, Radial Basis Functions: Theory and Implementations (Cambridge University Press, Cambridge, 2003)zbMATHCrossRefGoogle Scholar
  93. 93.
    W. Hendrickx, T. Dhaene, Sequential design and rational metamodelling, in Proc. Winter Simulation Conf., Orlando, FL, 2005Google Scholar
  94. 94.
    F.D. Bernardinis, M.I. Jordan, A.S. Vincentelli, Support vector machines for analog circuit performance representation, in Proc. Des. Autom. Conf., Anaheim, CA, 2003Google Scholar
  95. 95.
    M. Barros, J. Guilherme, N. Horta, GA-SVM feasibility model and optimization, in ACM Great Lakes Symp. VLSI, Stresa-Lago Maggiore, 2007Google Scholar
  96. 96.
    G. Alpaydin, S. Balkir, G. Dundar, An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7(3), 240–252 (2003)CrossRefGoogle Scholar
  97. 97.
    K.H. Lee, First Course on Fuzzy Theory and Applications (Springer Science & Business Media, Berlin, 2006)Google Scholar
  98. 98.
    T. McConaghy, K. Breen, J. Dyck, A. Gupta, Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide (Springer, New York, 2013)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Instituto Superior TécnicoInstituto de TelecomunicaçõesLisbonPortugal
  2. 2.Instituto Politécnico de TomarInstituto de TelecomunicaçõesLisbonPortugal

Personalised recommendations