Advertisement

Introduction

Chapter
  • 226 Downloads

Abstract

This chapter presents a brief introduction on the problematic addressed by this book, namely the impact of variability effects at nanometer-scale technology nodes and how an early prediction of the yield helps improving analog integrated circuits production cycles. Additionally, the main goals for the work presented in this book as well as the document’s structure are also highlighted in this chapter.

Keywords

Analog IC design Electronic design automation Parametric yield Monte Carlo analysis 

References

  1. 1.
    G. Gielen, Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies, in Proc. ASP-DAC’07 Des. Automat. Conf., 2007Google Scholar
  2. 2.
    M. Barros, J. Guilherme, N. Horta, Analog Circuits and Systems Optimization Based on Evolutionary Computation Techniques (Springer-Verlag, Berlin, 2010)CrossRefGoogle Scholar
  3. 3.
    P. Gupta, E. Papadopoulou, Yield analysis and optimization, in Handbook of Algorithms for Physical Design Automation, (CRC Press, Boca Raton, FL, 2008), pp. 771–790CrossRefGoogle Scholar
  4. 4.
    C. McAndrew, I.-S. Lim, B. Braswell, D. Garrity, Corner models: inaccurate at best, and it only gets worst…, in Proc. IEEE Custom Integr. Circuits Conf., 2013Google Scholar
  5. 5.
    C. Chiang, J. Kawa, Design for Manufacturability and Yield for Nano-Scale CMOS (Springer, Dordrecht, 2007)Google Scholar
  6. 6.
    A. Singhee, R.A. Rutenbar, Why quasi-Monte Carlo is better than Monte Carlo or Latin hypercube sampling for statistical circuit analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11), 1763–1776 (2010)CrossRefGoogle Scholar
  7. 7.
    IEEE IRDS, The International Roadmap for Devices and Systems: 2017, IEEE, 2017Google Scholar
  8. 8.
    G. Moretti, Senior Editor Chip Design Magazine, Complexity of Mixed-Signal Designs, 28 Aug 2014. [Online]. Available: http://chipdesignmag.com/sld/blog/2014/08/28/complexity-of-mixed-signal-designs/. Accessed 16 Sept 2018
  9. 9.
    IC Insights, Analog IC Market Forecast With Strongest Annual Growth Through 2022, 12 Jan 2018. [Online]. Available: http://www.icinsights.com/data/articles/documents/1036.pdf. Accessed 16 Sept 2018
  10. 10.
    N. Lourenço, R. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects (Springer International Publishing, Cham, 2017)CrossRefGoogle Scholar
  11. 11.
    R. Lourenço, N. Lourenço, N. Horta, AIDA-CMK: Multi-Algorithm Optimization Kernel Applied to Analog IC Sizing (Springer International Publishing, Cham, 2015)CrossRefGoogle Scholar
  12. 12.
    N. Lourenço, R. Martins, A. Canelas, R. Póvoa, N. Horta, AIDA: layout-aware analog circuit-level sizing with in-loop layout generation. Integration VLSI J. 55, 316–329 (2016)CrossRefGoogle Scholar

Copyright information

© Springer Nature Switzerland AG 2020

Authors and Affiliations

  1. 1.Instituto Superior TécnicoInstituto de TelecomunicaçõesLisbonPortugal
  2. 2.Instituto Politécnico de TomarInstituto de TelecomunicaçõesLisbonPortugal

Personalised recommendations