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A Synergistic Framework for Hardware IP Privacy and Integrity Protection pp 97–134Cite as

Fault Attack Protection and Evaluation

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Abstract

Fault attacks can obstruct the normal system execution by injecting errors into the hardware. By radiating the critical circuit components with high energy particle strikes, voltage transients are created to make the circuit malfunction temporarily. In recent years, fault attacks have demonstrated a great capability of leaking the cryptographics keys, and nullifying the entire system security mechanisms. The chapter introduces two protection schemes, including a new security primitive, i.e., public physical unclonable function (PPUF), that has provable time gap between the execution and simulation (ESG) to derive security, and a new analysis framework to identify critical circuit components for general purpose processors and guide the design optimization.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

    Meng Li & David Z. Pan

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  1. Meng Li
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  2. David Z. Pan
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Li, M., Pan, D.Z. (2020). Fault Attack Protection and Evaluation. In: A Synergistic Framework for Hardware IP Privacy and Integrity Protection. Springer, Cham. https://doi.org/10.1007/978-3-030-41247-0_4

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  • DOI: https://doi.org/10.1007/978-3-030-41247-0_4

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  • Print ISBN: 978-3-030-41246-3

  • Online ISBN: 978-3-030-41247-0

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