Skip to main content
SpringerLink
Log in

Hardware Design of 8 × 8 and 16 × 16 2D Discrete Cosine Transform with N/2 Equations for Image Compression

  • Conference paper
  • First Online:
4th International Conference on Internet of Things and Connected Technologies (ICIoTCT), 2019 (ICIoTCT 2019)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 1122))

  • 674 Accesses

Abstract

The discrete cosine transform (DCT) has remarkable significance in the area of image and video compression due to its energy compaction property. This paper propose a distinct architecture for 8 × 8 and 16 × 16 2D-DCT for compression of images. A method is proposed to reduce the number of equations with the help of high energy compaction property of DCT. In the conventional N point, 1D-DCT requires N number of equations for the transformation, by using high energy compaction property, only N/2 equations are required to perform the task. Proposed architecture reduces the arithmetic complexity. Further, it exhibits low power consumption with less area requirement. The proposed 2D-DCT is synthesized in XC3S700AN and XC6VLX75T devices, and the simulation results are compared with conventional 2D-DCT. The quality of the reconstructed image is evaluated by peak signal to noise ratio (PSNR). The obtained result shows the 75% reduction in the number of pixels required to store the image.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Potluri, U.S., Madanayake, A., Cintra, R.J., Bayer, F.M., Kulasekera, S., Edirisuriya, A.: Improved 8-point approximate DCT for image and video compression requiring only 14 additions. IEEE Trans. Circuits Syst. I Regul. Pap. 61(6), 1727–1740 (2014)

    Article  Google Scholar 

  2. Jridi, M., Alfalou, A., Meher, P.K.: A generalized algorithm and reconfigurable architecture for efficient and scalable orthogonal approximation of DCT. IEEE Trans. Circuits Syst. I Regul. Pap. 62(2), 449–457 (2015)

    Article  Google Scholar 

  3. Brahimi, N., Bouguezel, S.: An efficient fast integer DCT transform for images compression with 16 additions only. In: International Workshop on Systems, Signal Processing and their Applications, WOSSPA, pp. 71–74. IEEE (2011)

    Google Scholar 

  4. An, S., Wang, C.: Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform. IET Image Process. 2(6), 286–294 (2008)

    Article  MathSciNet  Google Scholar 

  5. Sateesh, S.V.V., Sakthivel, R., Nirosha, K., Kittur, H.M.: An optimized architecture to perform image compression and encryption simultaneously using modified DCT algorithm. In: 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies, pp. 442–447. IEEE (2011)

    Google Scholar 

  6. Madanayake, A., Cintra, R.J., Onen, D., Dimitrov, V.S., Rajapaksha, N., Bruton, L.T., Edirisuriya, A.: A row-parallel 8 × 8 2-D DCT architecture using algebraic integer-based exact computation. IEEE Trans. Circuits Syst. Video Technol. 22(6), 915–929 (2012)

    Article  Google Scholar 

  7. Masera, M., Martina, M., Masera, G.: Adaptive approximated DCT architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 27(12), 2714–2725 (2017)

    Google Scholar 

  8. Dhandapani, V.A., Ramachandran, S.: Area and power efficient DCT architecture for image compression. EURASIP J. Adv. Signal Process. 180(1), 1–9 (2014)

    Google Scholar 

  9. Gonzalez, R.C., Woods, R.E., Masters, B.R.: Digital Image Processing 3rd edn. (2009). J. Biomed. Opt. 14(2), 029901

    Article  Google Scholar 

  10. El-Banna, H., El-Fattah, A.A., Fakhr, W.: An efficient implementation of the 1D DCT using FPGA technology. In: Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No. 03CH37442), pp. 278–281. IEEE (2003)

    Google Scholar 

  11. Patiño, A.M., Peiró, M.M., Ballester, F., Paya, G.: 2D-DCT on FPGA by polynomial transformation in two-dimensions. In: 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), vol. 3, pp. III-365. IEEE (2004)

    Google Scholar 

  12. Trainor, D.W., Heron, J.P., Woods, R.F.: Implementation of the 2D DCT using a Xilinx XC6264 FPGA. In: 1997 IEEE Workshop on Signal Processing Systems. SiPS 1997 Design and Implementation formerly VLSI Signal Processing, pp. 541–550. IEEE (1997)

    Google Scholar 

  13. Edirisuriya, A., Madanayake, A., Dimitrov, V.S., Cintra, R.J., Adikari, J.: VLSI architecture for 8-point AI-based Arai DCT having low area-time complexity and power at improved accuracy. J. Low Power Electron. Appl. 2(2), 127–142 (2012)

    Article  Google Scholar 

  14. Kitsos, P., Voros, N.S., Dagiuklas, T., Skodras, A.N.: A high speed FPGA implementation of the 2D DCT for ultra high definition video coding. In: 2013 18th International Conference on Digital Signal Processing (DSP), pp. 1–5. IEEE (2013)

    Google Scholar 

  15. Khayam, S.A.: The discrete cosine transform (DCT): theory and application, Department of Electrical and Computer Engineering, Michigan State University, Lansing, MI, USA, Technical report, ECE, pp. 602–802 (2003)

    Google Scholar 

  16. Jridi, M., Meher, P.K.: Scalable approximate DCT architectures for efficient HEVC-compliant video coding. IEEE Trans. Circuits Syst. Video Technol. 27(8), 1815–1825 (2017)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Telecommunication, NIT, Raipur, India

    Nikhil C. Bichwe

  2. Department of Electronics and Communication Engineering, MNIT, Jaipur, India

    Rahul Kumar Chaurasiya

Authors
  1. Nikhil C. Bichwe
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rahul Kumar Chaurasiya
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Nikhil C. Bichwe .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Malaviya National Institute of Technology, Jaipur, Rajasthan, India

    Neeta Nain

  2. Department of Computer Science and Engineering, Malaviya National Institute of Technology, Jaipur, Rajasthan, India

    Santosh Kumar Vipparthi

Rights and permissions

Reprints and permissions

Copyright information

© 2020 The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Bichwe, N.C., Chaurasiya, R.K. (2020). Hardware Design of 8 × 8 and 16 × 16 2D Discrete Cosine Transform with N/2 Equations for Image Compression. In: Nain, N., Vipparthi, S. (eds) 4th International Conference on Internet of Things and Connected Technologies (ICIoTCT), 2019. ICIoTCT 2019. Advances in Intelligent Systems and Computing, vol 1122. Springer, Cham. https://doi.org/10.1007/978-3-030-39875-0_26

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-39875-0_26

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-39874-3

  • Online ISBN: 978-3-030-39875-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation