Abstract
Bose-Chaudhuri-Hocquenghem (BCH) code is normally utilized in communication systems in order to enhance its reliability. The main computational complexity and high power consumption stages in BCH come from its two main stages, the key equation solving (KES) and Chien search (CS). This paper presents two different algorithms to reduce the computational process and hence reduce the total power consumption. These algorithms are the verification algorithm and the two-step parallel CS architecture which are utilized in KES and CS stages, respectively. The whole proposed system is implemented using LABVIEW tools from NI. The results show that the proposed BCH algorithm provides an enhanced performance when compared to the conventional one.
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Shebl, N.K., Eisa, S.M., Issa, H.H., Shehata, K.A. (2020). Low Power BCH Decoder Using Verification Algorithm and Two-Step Parallel Chien Search Architecture. In: Arai, K., Kapoor, S., Bhatia, R. (eds) Advances in Information and Communication. FICC 2020. Advances in Intelligent Systems and Computing, vol 1129. Springer, Cham. https://doi.org/10.1007/978-3-030-39445-5_4
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DOI: https://doi.org/10.1007/978-3-030-39445-5_4
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