Abstract
Recent internet traffic growth becomes a serious problem for internet routers from the aspects of both packet processing throughput and power consumption. Packet Processing Cache (PPC) is one of the promising approaches to solve this problem. PPC caches table lookup results in packet processing and enables to reduce the number of TCAM (Ternary Content Addressable Memory) accesses, which are known as the major cause of degrading the throughput and power efficiency of packet processing. Although PPC can process a packet at fast with significant low energy if the packet hits in the cache, the cache miss rate of PPC is still high due to the small cache capacity. Furthermore, because conventional PPC has no tolerance to attacks, the cache miss rate of PPC is drastically increased when attacking. For these problems, we propose two different cache architecture, called Port-aware Cache and Victim IP Cache. Our simulation showed that the combination of them can achieve 1.81x higher throughput with 45% smaller energy per packet when compared to conventional PPC.
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This work was supported by JSPS KAKENHI Grant Number JP18K18022.
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Yamaki, H. (2020). Efficient Cache Architecture for Packet Processing in Internet Routers. In: Arai, K., Kapoor, S., Bhatia, R. (eds) Advances in Information and Communication. FICC 2020. Advances in Intelligent Systems and Computing, vol 1129. Springer, Cham. https://doi.org/10.1007/978-3-030-39445-5_26
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DOI: https://doi.org/10.1007/978-3-030-39445-5_26
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