Abstract
Due to its complexity, the physical design process is divided into several primary steps. Having introduced in Chap. 4 the flow, constraints and methodologies of today’s physical design process, we now investigate the various steps required to generate its output: a layout. These steps, which transform a netlist into optimized mask data, are dealt with one by one in this chapter. A layout is generated from a netlist. We first describe how a netlist is created, that is, either by using hardware description languages (HDLs) in digital design (Sect. 5.1), or by deriving it from a schematic, as is common in analog design (Sect. 5.2). Then the physical design steps, comprising partitioning, floorplanning, placement, and routing, are presented in detail (Sect. 5.3). All of these steps are supported by highly sophisticated EDA tools in the case of digital designs, which is our focus here. We also discuss in this section the key aspects of symbolic compaction, standard-cell design and PCB design. When the physical design phase is completed, the resulting layout must be verified. This verification step confirms both functional correctness and design manufacturability. Methodologies and tools for comprehensive design verification, with a focus on physical verification, are covered in Sect. 5.4. Finally, we briefly touch on layout post-processing methodologies, such as resolution enhancement techniques (RET), that might impact physical design (Sect. 5.5).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
IEEE Standard 91-1984, IEEE Standard Graphic Symbols for Logic Functions, and IEEE Standard 91a-1991, Supplement to IEEE Standard 91-1984.
- 2.
IEC 60617 Graphical symbols for diagrams.
- 3.
The so-called “Pentium FDIV bug” is an infamous example, where a well-simulated Intel processor returned incorrect binary floating-point results when dividing a number, causing a $475 million loss for Intel [6].
- 4.
It is important to note why we do not take any other layout information into account, such as library information. This would, of course, greatly simplify the task and speed up netlist recognition. However, any error in the library would then be considered as well. The final netlist check would then check identical netlists as both lists would be affected by the same library-based error(s). This would render the LVS useless.
- 5.
Additional parasitic coupling effects are caused by the chip substrate, which is common to all devices. However, these effects are not considered in all simulation tools.
References
R.J. Baker, CMOS circuit design, layout, and simulation, in IEEE Press Series on Microelectronic Systems, 3rd edn. (Wiley-IEEE Press, 2010). ISBN 978-0470881323
M.R. Barbacci, A comparison of register transfer languages for describing computers and digital systems. Technical Report (Carnegie Mellon University Research Showcase @ CMU, Department of Computer Science, 1973)
E. Christen, K. Bakalar, VHDL-AMS-a hardware description language for analog and mixed-signal applications. IEEE Trans. Circuits Syst. II Analog. Digit. Signal Process. 46(10), 1263–1272 (1999)
W.C. Elmore, The transient response of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. 19, 55–63 (1948). https://doi.org/10.1063/1.1697872
K. Golshan, Physical Design Essentials (Springer, 2007). ISBN 978-0-387-36642-5. https://doi.org/10.1007/978-0-387-46115-1
T.R. Halfhill, An error in a lookup table created the infamous bug in Intel’s latest processor. BYTE (20), 163–164 (1995)
M.Y. Hsueh, Symbolic layout compaction, in Computer Design Aids for VLSI Circuits, ed. by P. Antognetti, D.O. Pederson, H. de Man. NATO ASI Series (Series E: Applied Sciences), vol. 48 (Springer, 1984). ISBN 978-94-011-8008-5. https://doi.org/10.1007/978-94-011-8006-1_11
D. Jansen et al., The Electronic Design Automation Handbook (Springer, 2003). ISBN 978-14-020-7502-5. https://doi.org/10.1007/978-0-387-73543-6
A. Kahng, J. Lienig, I. Markov et al., VLSI Physical Design: From Graph Partitioning to Timing Closure (Springer, 2011). ISBN 978-90-481-9590-9. https://doi.org/10.1007/978-90-481-9591-6
L. Lavagno, G. Martin, L. Scheffer, Electronic Design Automation for Integrated Circuits Handbook (CRC Press, 2006). ISBN 978-0849330964
L. Liebmann, Layout impact of resolution enhancement techniques: impediment or opportunity?, in International Symposium on Physical Design (ISPD) (2003), pp. 110–117. https://doi.org/10.1145/640000.640026
J. Lienig, H. Bruemmer, Fundamentals of Electronic Systems Design (Springer, 2017). ISBN 978-3-319-55839-4. https://doi.org/10.1007/978-3-319-55840-0
B. Murphy, M. Pandey, S. Safarpour, Finding Your Way Through Formal Verification (CreateSpace Independent Publishing Platform, 2018). ISBN 978-1986274111
S.M. Sait, H. Youssef, VLSI Physical Design Automation, Theory and Practice (World Scientific, 1999)
P. Spindler, Personal communication (TU Munich, 2008)
B. Yu, D.Z. Pan, Design for Manufacturability with Advanced Lithography (Springer, 2016). ISBN 978-3-319-20384-3. https://doi.org/10.1007/978-3-319-20385-0
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Lienig, J., Scheible, J. (2020). Steps in Physical Design: From Netlist Generation to Layout Post Processing. In: Fundamentals of Layout Design for Electronic Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-39284-0_5
Download citation
DOI: https://doi.org/10.1007/978-3-030-39284-0_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-39283-3
Online ISBN: 978-3-030-39284-0
eBook Packages: EngineeringEngineering (R0)