Abstract
This chapter gives a sound introduction to the technologies, tasks and methodologies used to design the layout of an electronic circuit. With this basic design knowledge as a foundation, the subsequent chapters then delve deeper into specific constraints and aspects of physical design, such as semiconductor technologies (Chap. 2 ), interfaces, design rules and libraries (Chap. 3 ), design flows and models (Chap. 4 ), design steps (Chap. 5 ), analog design specifics (Chap. 6 ), and finally reliability measures (Chap. 7 ). In Sect. 1.1, we introduce several of the most common fabrication technologies for electronic systems. The central topic of this book is the physical design of integrated circuits (aka chips, ICs) but hybrid technologies and printed circuit boards (PCBs) are also considered. In Sect. 1.2 of our introduction, we examine in more detail the significance and peculiarities of this related branch of modern electronics—also known as microelectronics. In Sect. 1.3, we then consider the physical design of both integrated circuits and printed circuits boards with a specific emphasis on their primary design steps. After these opening sections, we close the introductory chapter in Sect. 1.4 by presenting our motivation for this book and describing the organization of the chapters that follow.
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- 1.
Sputtering is a physical process whereby microscopic particles of a solid material are ejected from its surface by bombarding the solid with high-energy ions.
- 2.
While the term “front-end-of-line” (FEOL) refers to the first portion of any IC fabrication where the individual devices are patterned, “back-end-of-line” (BEOL) comprises the subsequent deposition of metal interconnect layers. Both are discussed in Chap. 2.
- 3.
Bipolar transistors are devices whose operation depends on the two types of charge carriers (electrons and holes). We will cover these devices and their operation more fully in Chap. 6.
- 4.
We should mention here that downscaling to lower technology nodes in semiconductor fabrication has reached a point where aging effects are becoming increasingly critical. One of the more acute concerns is interconnect degradation by migration effects, in which the electrical current flowing through the IC can slowly erode the miniature physical structures. Preventive measures for these effects are needed especially in the physical design flow. We shall deal with this topic fully in Chap. 7.
- 5.
CMOS is an acronym for “complementary metal oxide silicon”. CMOS technology incorporates two complementary n-type and p-type unipolar transistors, which are manufactured as metal-oxide-silicon layers. We will cover them in detail in Chap. 2.
- 6.
DMOS stands for “double diffused metal oxide silicon”. This is a fabrication technology for unipolar transistors that switch large currents in power electronics. We can implement exceptionally low on-state resistances on the order of mΩ with DMOS transistors.
- 7.
Designing with standard cells is a very efficient and hence popular design flow for ICs. We will introduce and discuss standard cells and design flows in Chap. 4.
- 8.
- 9.
This statement applies to structure sizes greater than approximately 20 nm. For smaller sizes, a different internal structure is required for unipolar transistors. FinFETs—which are beyond the scope of this book—are used in this case.
- 10.
We use “devices/IC” and not, like most other authors, “transistors/IC” as a unit of scale, as many other types of devices besides transistors are used in mixed processes. The data for “transistors/IC” and “devices/IC” is almost the same for logic chips, though.
- 11.
Matching—a technique used in analog chip layout—plays a key role here. We shall discuss this very important topic fully in Chap. 6.
References
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R. Fischbach, J. Lienig, T. Meister, From 3D circuit technologies and data structures to interconnect prediction, in Proceedings of 2009 International Workshop on System Level Interconnect Prediction (SLIP) (2009), pp. 77–84. https://doi.org/10.1145/1572471.1572485
J. Kilby, Patent No. US3138743: Miniaturized electronic circuits. Patent filed Feb. 6, 1959, published June 23, 1964
G.E. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965). https://doi.org/10.1109/N-SSC.2006.4785860
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https://en.wikipedia.org/wiki/Transistor_count. Accessed 1 Jan 2020
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Lienig, J., Scheible, J. (2020). Introduction. In: Fundamentals of Layout Design for Electronic Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-39284-0_1
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DOI: https://doi.org/10.1007/978-3-030-39284-0_1
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