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Improved Crypto Algorithm for High-Speed Internet of Things (IoT) Applications

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Intelligent Computing Paradigm and Cutting-edge Technologies (ICICCT 2019)

Part of the book series: Learning and Analytics in Intelligent Systems ((LAIS,volume 9))

Abstract

Modern technologies focus on integrated systems based on the Internet of Things (IoT). IoT based devices are unified with various levels of high-speed internet communication, computation process, secure authentication and privacy policies. One of the significant demands of present IoT is focused on its secure high-speed communication. However, traditional authentication and secure communication find it very difficult to manage the current need for IoT applications. Therefore, the need for such a reliable high-speed IoT scheme must be addressed. This proposed title introduces an enhanced version of the Rijndael Cryptographic Algorithm (Advanced Encryption Standard – AES) to obtain fast-speed IoT-based application transmission. Pipeline-based AES technique promises for the high-speed crypto process, and this secure algorithm targeted to fast-speed Field Programmable Gate Array (FPGA) hardware. Thus, high-speed AES crypto algorithms, along with FPGA hardware, will improve the efficiency of future IoT design. Our proposed method also shows the tradeoff between High-Speed communications along with various FPGA platforms.

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References

  1. Daemen, J., Rijmen, V.: The Design of Rijndael: AES the Advanced Encryption Standard, 1st edn. Springer, Heidelberg (2002)

    Book  Google Scholar 

  2. Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Cryptographic Hardware and Embedded Systems - CHES 2005, pp. 427–440 (2005)

    Chapter  Google Scholar 

  3. Zhang, X., Parhi, K.: High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(9), 957–967 (2004)

    Article  Google Scholar 

  4. Kaur, S., Vig, R.: Efficient implementation of AES algorithm in FPGA device. In: International Conference on Computational Intelligence & Multimedia Applications (2007)

    Google Scholar 

  5. Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.D.: Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: ITCC 2004, pp. 583–587 (2004)

    Google Scholar 

  6. FIPS 197, Advanced Encryption Standard (AES) (2001)

    Google Scholar 

  7. Saggese, G.P., Mazzeo, A., Mazocca, N., Strollo, A.G.M.: An FPGA based performance analysis of the unrolling, tiling and pipelining of the AES algorithm. In: FPL (2003)

    Chapter  Google Scholar 

  8. Hodjat, A., Verbauwhede, I.: A 21.54 Gbits fully pipelined processor on FPGA. In: IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 308–309 (2004)

    Google Scholar 

  9. Rashtchi, V., Mosavi, S.H.: Strengthened of AES encryption algorithm within the new logic topology. Mail. J. Electr. Eng. 12(1), 87–94 (2018)

    Google Scholar 

  10. Carlet, C., Goubin, L., Prouff, E., Quisquater, M., Rivain, M.: Higher order masking schemes for S-boxes. LNCS, vol. 7549, pp. 366–384 (2012)

    Chapter  Google Scholar 

  11. Ye, Y., Wu, N., Zhang, X., Dong, L., Zhou, F.: An optimized design for compact masked AES S-Box based on composite field and common subexpression elimination algorithm. J. Circ. Syst. Comput. 27(11), 1850171 (2018)

    Article  Google Scholar 

  12. Sakthivel, R., Vanitha, M., Kittur, H.M.: Low power high throughput reconfigurable stream cypher hardware VLSI architectures. Int. J. Inf. Comput. Secur. 6(1), 1–11 (2014)

    Google Scholar 

  13. Abdellatif, K.M., Chotin-Avot, R., Mehrez, H.: Low-cost solutions for secure remote reconfiguration of FPGAs. Int. J. Embed. Syst. 6(2/3), 257–265 (2014)

    Article  Google Scholar 

  14. Gaspar, L., Drutarovsky, M., Fischer, V., Bochard, N.: Efficient AES S-boxes implementation for non-volatile FPGAS. IEEE Transaction Paper, pp. 649–653 (2009)

    Google Scholar 

  15. Wong, M.M., Wong, M., Zhang, C., Hijazin, I.: Circuit and system design for optimal lightweight AES encryption on FPGA. IAENG Int. J. Comput. Sci. 45(1), 52–62 (2018)

    Google Scholar 

  16. Kshirsagar, R.V., Vyawahare, M.V.: FPGA implementation of high-speed VLSI architectures for AES algorithm. In: IEEE Conference on Emerging Trends in Engineering and Technology (2012)

    Google Scholar 

  17. Chakrabarti, S., Samanta, D.: Image steganography using priority-based neural network and pyramid. Emerg. Res. Comput. Inf. Commun. Appl., 163–172 (2016). https://doi.org/10.1007/978-981-10-0287-8_15

    Google Scholar 

  18. Ghosh, G., Samanta, D., Paul, M.: Approach of message communication based on twisty “Zig-Zag”. In: 2016 International Conference on Emerging Technological Trends (ICETT) (2016). https://doi.org/10.1109/icett.2016.7873676

  19. Hossain, M.A., Samanta, D., Sanyal, G.: Extraction of panic expression depending on lip detection. In: 2012 International Conference on Computing Sciences (2012). https://doi.org/10.1109/iccs.2012.35

  20. Hossain, M.A., Samanta, D., Sanyal, G.: Statistical approach for extraction of panic expression. In: 2012 Fourth International Conference on Computational Intelligence and Communication Networks (2012). https://doi.org/10.1109/cicn.2012.189

  21. Khadri, S.K.A., Samanta, D., Paul, M.: Approach of message communication using fibonacci series. In: Cryptology. Lecture Notes on Information Theory (2014). https://doi.org/10.12720/lnit.2.2.168-171

  22. Choi, S.-K., Ko, J.-S., Kwak, J.: A study on IoT device authentication protocol for high speed and lightweight. In: Proceedings of the International Conference on Platform Technology and Service, PlatCon 2019 (2019). https://doi.org/10.1109/PlatCon.2019.8669418

  23. Jindal, F., Mudgal, S., Choudhari, V., Churi, P.P.: Emerging trends in Internet of Things. Inf. Technol. Trends Emerg. Technol. Artif. Intell., 50–60 (2019). https://doi.org/10.1109/CTIT.2018.8649535

  24. Borkar, A.M., Kshirsagar, R., Vyawahare, M.: FPGA implementation of AES algorithm. In: 3rd International Conference on Electronics Computer Technology (ICECT), vol. 3, pp. 401–405 (2011)

    Google Scholar 

  25. Algredo-Badillo, I., Feregrino-Uribe, C., Cumplido, R., Morales-Sandoval, M.: FPGA implementation and performance evaluation of AES-CCM cores for wireless networks. In: International Conference on Reconfigurable Computing and FPGAs, pp. 421–426 (2008)

    Google Scholar 

  26. Saravanan, S., Hailu, M., Gouse, G.M., Lavanya, M., Vijaysai, R.: Optimized secure scan flip flop to thwart side channel attack in crypto-chip. In: Zimale, F., Enku Nigussie, T., Fanta, S. (eds.) Advances of Science and Technology, ICAST 2018. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol. 274. Springer, Cham (2019)

    Google Scholar 

  27. Saravanan, S., Hailu, M., Gouse, G.M., Lavanya, M., Vijaysai, R.: Design and analysis of low-transition address generator. In: Zimale, F., Enku Nigussie, T., Fanta, S. (eds.) Advances of Science and Technology, ICAST 2018. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol. 274. Springer, Cham (2019)

    Google Scholar 

  28. Mohammed Gouse, G., Haji, C.M., Saravanan: Improved reconfigurable based lightweight crypto algorithms for IoT based applications. J. Adv. Res. Dyn. Control Syst. 10(12), 186–193 (2018)

    Google Scholar 

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Correspondence to Mohammed Gouse Galety .

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Galety, M.G., Al Atroshi, C., Arul Kumar, N., Saravanan (2020). Improved Crypto Algorithm for High-Speed Internet of Things (IoT) Applications. In: Jain, L., Peng, SL., Alhadidi, B., Pal, S. (eds) Intelligent Computing Paradigm and Cutting-edge Technologies. ICICCT 2019. Learning and Analytics in Intelligent Systems, vol 9. Springer, Cham. https://doi.org/10.1007/978-3-030-38501-9_28

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