Abstract
The chapter is devoted to hardware reduction based on combining twofold state assignment with replacement of logical conditions. Embedded memory blocks are used for executing the replacement. The replacement for Moore FSMs is based on encoding of the classes of pseudoequivalent states. There is discussed the possibility of transformation of initial GSA allowing decreasing the number of additional variables. Next, these methods are discussed for both Mealy and Moore FSMs. Also, it is shown how to combine these two methods with encoding of the collections of microoperations. The last part of the chapter is devoted to synthesis methods based on transformation of initial GSA.
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Barkalov, A., Titarenko, L., Mielcarek, K., Chmielewski, S. (2020). Combining Twofold State Assignment with Replacement of Logical Conditions. In: Logic Synthesis for FPGA-Based Control Units. Lecture Notes in Electrical Engineering, vol 636. Springer, Cham. https://doi.org/10.1007/978-3-030-38295-7_6
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DOI: https://doi.org/10.1007/978-3-030-38295-7_6
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