Abstract
Since multiple voltage levels are required simultaneously by the proposed wearable device in Fig. 1.12, multiple voltage regulators are needed. The switched capacitor (SC) voltage regulator is widely utilized in low power applications since the small capacitance can be fully integrated on-chip while driving μA current. Conventionally, multiple SC voltage regulators are required to generate simultaneous multiple regulated voltage levels. This way, each block in the chip operates at an optimum voltage level. However, this conventional PMU design suffers from a large area overhead because it is dominated by the area of the SC regulators. The number of SC regulators increases as the number of the required regulated output voltage levels increases. Hence, more passive components (flying and load capacitors) are needed which makes the PMU area large. As a result, it is imperative to find an efficient way to generate multiple output voltages with minimum area overhead that targets μW power devices.
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Appendix: Verilog Code of ATM
Appendix: Verilog Code of ATM
module FSM (En1,En2,En3,En4,g,a,b,c,clk,rst,state,next-state); input a, b, c ;input rst, clk;output reg En1, En2, En3, En4, g; output reg [1:0] state;output reg [1:0] next-state;parameter [1:0] S0=2’b00, S1=2’b01, S2=2’b11;always @ (a or b or c or state)begincase (state)S0: case (a,b,c) 3’b000: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b001: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b010: begin next-state=S1; En1= 1; En2= 1; g=1; En3=0; En4=1; end
3’b100: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b101: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b110: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
default: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
endcase
S1: case (a,b,c)3’b000: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b001: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b010: begin next-state=S2; En1= 0; En2= 1; g=1; En3=0; En4=1; end
3’b011: begin next-state=S1; En1= 1; En2= 1; g=1; En3=0; En4=1; end
3’b100: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b110: begin next-state=S1; En1= 1; En2= 1; g=1; En3=0; En4=1; end
default: begin next-state=S1; En1= 1; En2= 1; g=1; En3=0; En4=1; end
endcase
S2: case (a,b,c)3’b000: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b001: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b010: begin next-state=S2; En1= 0; En2= 1; g=1; En3=0; En4=1; end
3’b011: begin next-state=S2; En1= 0; En2= 1; g=1; En3=0; En4=1; end
3’b100: begin next-state=S0; En1= 1; En2= 0; g=0; En3=1; En4=0; end
3’b110: begin next-state=S2; En1= 0; En2= 1; g=1; En3=0; En4=1; end
3’b110: begin next-state=S2; En1= 0; En2= 1; g=1; En3=0; En4=1; end
default: begin next-state=S2; En1= 0; En2= 1; g=1; En3=0; En4=1; end
endcase
endcase end
always @ (posedge clk or negedge rst)
if (rst==0)state< =S0;
else state< =next-state;
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Kilani, D., Mohammad, B., Alhawari, M., Saleh, H., Ismail, M. (2020). Dual-Outputs Switched Capacitor Voltage Regulator. In: Power Management for Wearable Electronic Devices. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-030-37884-4_4
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DOI: https://doi.org/10.1007/978-3-030-37884-4_4
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