Abstract
Finite State Machine (FSM) is a tool for designing sequential logic circuits by defining states. The general models of Moore and Mealy machines are presented. The design of Sequence detector using Moore and Mealy machines are explained and illustrated with an example. The preparation of algorithmic state machine chart and the application of state reduction techniques (Row elimination and Implication table methods) are also illustrated with examples.
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Natarajan, D. (2020). Design of Sequential Logic Circuits. In: Fundamentals of Digital Electronics. Lecture Notes in Electrical Engineering, vol 623. Springer, Cham. https://doi.org/10.1007/978-3-030-36196-9_13
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DOI: https://doi.org/10.1007/978-3-030-36196-9_13
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