Abstract
This chapter consists of a brief review or introduction, depending on the reader’s background, of the basics of computer arithmetic. The first two sections are on algorithms and designs of hardware units for addition and multiplication. (Subtraction is another fundamental operation, but it is almost always realized as the addition of the negation of the subtrahend.) For each of the two operations, a few architectures for hardware implementation are sketched that are sufficiently exemplary of the variety of possibilities. The third section of the chapter is on division, an operation that in its direct form is (in this book) not as significant as addition and multiplication but which may nevertheless be useful in certain cases. The discussions on algorithms and architectures for division are therefore limited.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
For brevity, we shall make a distinction between a number and its representation only if confusion is possible.
- 2.
Modular arithmetic is discussed in subsequent chapters.
- 3.
The chain may be viewed as consisting of “switches” that are much faster than “standard” logic gates.
- 4.
All these provide good examples of the limitations in measuring operational time by simply counting gate delays.
- 5.
It should be noted that recent work has shown that for moderate precision, with proper realization a carry-ripple adder can be competitive with adders that are nominally much faster (i.e., with performance is measured in terms of gate delays) [19].
- 6.
The very high precisions of cryptography arithmetic require the combination of several techniques.
- 7.
The worst case is a linear structure that is essentially a carry-ripple adder.
- 8.
For convenience we assume that n is exactly divisible by m; if not, then one block may be made smaller or larger than m.
- 9.
It is reasonable to exclude inverter delay. It is also worth noting that in current technology a multiplexer can be realized with much greater efficiency (cost and performance) than is apparent from a direct gate-level derivation.
- 10.
For example, carry-skip adders, which we have not covered.
- 11.
Note the position of the apostrophe: ones’ vs. two’s. See [21] for an explanation.
- 12.
In manual arithmetic, the simplest method is this: scan the ones’-complement representation from the least significant bit to the most significant bit; copy every 0 and the first 1; thereafter invert every bit.
- 13.
The representation is used in standard floating-point representations.
- 14.
As indicated above, a prefix operator whose output is a final carry can be simplified. We use ∘ for the simplified version of •.
- 15.
Some authors use “partial product” to refer to what we term “multiplicand multiple.”
- 16.
- 17.
What follows is not always possible with similar algorithms in the modular arithmetic of cryptography (Chap. 5).
- 18.
A CSA is also known as a 3:2 compressor because it “compresses” three inputs into two outputs.
- 19.
Note that a CPA is not absolutely necessary. The assimilation can be done by cycling n times through the CSA, but that is a very slow method that, in practice, was abandoned in the late 1950s.
- 20.
One alternative is to use redundant representation for the “problematic” multiples.
- 21.
With a higher radix multiples that are not powers of two may be “pre-computed” by addition—e.g., 3x as 2x + x—or on-the-fly, in redundant representation [4].
- 22.
One-bit recoding as originally devised is commonly known as Booth’s Algorithm. The name is sometimes also applied to multiple-bit recoding.
- 23.
Just as the multiplication algorithms can be easily modified for n-bit multiplicand, m-bit multiplier, and n + m-bit product, so too can the division algorithms be modified for n + m-bit dividend, m-bit divisor, n-bit quotient, and m-bit remainder.
- 24.
- 25.
We have omitted some details; for example, the bit should be stored in, say, a flip-flop, as it is used to control the operation in the next cycle, not the current one.
- 26.
The second is skipping past 0s or 1s in the partial remainder (which in multiplication corresponds to skipping past 0s or 1s in the multiplier), and the third is taking several bits of the partial remainder at each step (which in multiplication corresponds to taking several bits of the multiplier at each step.)
- 27.
Arithmetic in “scientific” notation.
- 28.
See also Sect. 1.2.2.
- 29.
The basic nonrestoring algorithm can be formulated with the nonredundant digit set \(\{ \overline {1}, 1\}\), although there is little practical benefit in doing so.
- 30.
Note that the basic nonrestoring algorithm also “normalizes” the divisor d to d ∗ = 2nd.
- 31.
- 32.
This can be done in a small CPA or by using a lookup table.
- 33.
This is a simple diagram that omits some details that are related to control and timing. For example, in a given cycle, except the first, the quotient digit is used to select the divisor multiple (and arithmetic operation) in the subsequent cycle.
References
A. R. Omondi, 1994. Computer Arithmetic Systems. Prentice Hall, Hemel Hempstead, UK.
B. Parhami. 2000. Computer Arithmetic. Oxford University Press, Oxford, UK.
M. Ercegovac and T. Lang. 2004. Digital Arithmetic. Morgan Kaufmann, San Francisco, CA, USA.
M. J. Flynn and S. F. Oberman. 2001. Advanced Computer Arithmetic Design. Wiley-Interscience, New York, USA.
A. R. Omondi. 2015. Computer-Hardware Evaluation of Mathematical Functions. Imperial College Press, London, UK.
R. W. Doran, 1988. Variants on an improved carry-lookahead adder. IEEE Transactions on Computers, 37(9):1110–1113.
S. V. Lakshmivaran and S. K. Dhall, 1994. Parallel Computation Using the Prefix Problem. Oxford University Press, Oxford, UK.
R. P. Brent and H. T. Kung, 1982. A regular layout for parallel adders. IEEE Transactions on Computers, C-31(3):260–264.
R. E. Ladner and M. J. Fischer. 1980. Parallel prefix computation. Journal of the ACM, 27:831–838.
P. M. Kogge and H. S. Stone. 1973. A parallel algorithm for the efficient computation of a general class of recurrence relations. IEEE Transactions on Computers, 22:786–793.
S. Knowles. 1999. A family of adders. Proceedings, 14th Symposium on Computer Arithmetic, pp. 30–34.
T. Han and D. A. Carlson. 1987. Fast area-efficient VLSI adders. Proceedings, 8th International Symposium on Computer Arithmetic, pp. 49–56.
A. Beaumont-Smith and C.-C. Lim, 2001. “Parallel prefix adder design”. Proceedings, 15th International Symposium on Computer Arithmetic, pp. 218–225.
A. Tyagi. 1993. A reduced area scheme for carry-select adders. IEEE Transactions on Computers, 42(10):1163–1170.
G. A. Ruiz and M. Granda. 2004. An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit. Microelectronics Journal, 35:939–944.
M. D. Ercegovac and T. Lang. 1987. On-the-fly conversion of redundant into conventional representations. IEEE Transactions on Computers, C-36(7):895–897.
N. H. E. Weste and K. Eshraghian. 1994. Principles of CMOS VLSI Design. Addison-Wesley. Reading, Massachusetts, USA.
J. M. Rabaey. 1996. Digital Integrated Circuits. Prentice Hall, Saddle River, New Jersey, USA.
N. Burgess. 2013. Fast ripple-carry adders in standard-cell CMOS VLSI. Proceedings, 20th International Symposium on Computer Arithmetic, pp. 103–111.
X. Cui, W. Liu, S. Wang, E. E. Swartzlander, and E. Lombardi. 2018. Design of high-speed wide-word hybrid parallel-prefix/carry-select and skip adders. Journal of Signal Processing Systems, 90(3):409–419.
D. E. Knuth. 1998. The Art of Computer Programming, Vol. 2. Addison-Wesley, Reading, Massachusetts, USA.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
R. Omondi, A. (2020). Basic Computer Arithmetic. In: Cryptography Arithmetic. Advances in Information Security, vol 77. Springer, Cham. https://doi.org/10.1007/978-3-030-34142-8_1
Download citation
DOI: https://doi.org/10.1007/978-3-030-34142-8_1
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-34141-1
Online ISBN: 978-3-030-34142-8
eBook Packages: Computer ScienceComputer Science (R0)