Efficient RSA Crypto Processor Using Montgomery Multiplier in FPGA

Abstract

With the advancement of technology in data communication, security plays a major role in protecting user’s data from adversaries. Cryptography is a technique which consists of various algorithms to provide secure communication during data transfer. One of the most widely used and highly secure algorithm is RSA (Rivest, Adi Shamir and Leonard Adleman). This research is going to focus on designing an efficient crypto processor for RSA on Nexys4, a ready-to-use FPGA (Field Programmable Gate Array) board. There are various techniques in implementing RSA algorithm in hardware platforms. Primary concentration is to implement the algorithm in a high performant manner, and it will be achieved using Montgomery multiplication technique. RSA is a public key cryptography system which involves generation of public key for encryption and private key for decryption. Building blocks of RSA includes: Two multiplier blocks, two blocks to verify the primality of random numbers, one GCD (Greatest Common Divisor) block to check the validity of a public key, two modular exponential blocks – one is for generating encrypted or cipher message and another is to retrieve the original message from the cipher text. Simulation and synthesis of these blocks is achieved and verified using Xilinx Vivado Design Suite.