Abstract
In today’s scenario modern electronic systems are in need of compact digital circuits. So, miniaturization of circuits is rapidly growing area. The speed and power consumption of a digital circuit is determined by Flip-flops. The total number of transistors in the clock generation circuit indirectly reduced by the introduction of the pass transistor logic in the existing flip flop design, which also reduces the power consumption of the circuit due to transistor reduction. Reduction of number of transistors in flip-flop design leads to miniaturization of digital circuits. In this paper, the pulse triggered Flip-Flop (FF) for power efficiency is designed and discussed. The AND function in the clock generation circuitry is replaced with the PTL based AND gate circuit. The n-mos transistors are arranged in parallel using the PTL based AND gate and due to faster discharge of the pulse less power is consumed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Karimi, A., Rezai, A., Hajhashemkhani, M.M.: A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power. Integration 60, 160–166 (2018)
Lin, J.-F.: Low-power pulse-triggered flip-flop design based on a signal feed-through. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(1), 181–185 (2014)
Saranya, L., Arumugam, S.: Optimization of power for sequential elements in pulse triggered flip-flop using low power topologies. Int. J. Sci. Technol. Res. 2(3), 140–145 (2013)
Gupta, T., Mehra, R.: Efficient explicit pulsed double edge triggered flip-flop by using dependency on data. IOSR J. Electron. Commun. Eng. (IOSRJECE) 2(1), 01–07 (2012)
Sadrossadat, S., Mostafa, H., Anis, M.: Statistical design framework of sub-micron flip-flop circuits considering die-to-die and within-die variations. IEEE Trans. Semicond. Manuf. 24(2), 69–79 (2011)
Zhao, P., Darwish, T., Bayoumi, M.: High-performance and low power conditional discharge flip-flop. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(5), 477–484 (2004)
Zhao, P., McNeely, J.B., Golconda, P.K., Venigalla, S., Wang, N., Downey, L.: Clocked-pseudo-NMOS flip-flops for level conversion in dual supply systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(9), 1196–1202 (2009)
Mahmoodi, H., Tirumalashetty, V., Cooke, M., Roy, K.: Ultra low power clocking scheme using energy recovery and clock gating. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(1), 33–44 (2009)
Rasouli, S.H., Khademzadeh, A., Afzali-Kusha, A., Nourani, M.: Low-power single-and double-edge-triggered flip-flops for high-speed applications. IEEE Proc. Circuits Devices Syst. 152(2), 118–122 (2005)
Phyu, M.W., Goh, W.L., Yeo, K.S.: A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration. In: 2005 IEEE International Symposium on Circuits and Systems, pp. 2429–2432. IEEE (2005)
Tschanz, T., Narendra, S., Chen, Z., Borkar, S., Sachdev, M., De, V.: Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors. In: Proceedings International Symposium on Low Power Electronics and Design, pp. 207–212. IEEE (2001)
Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edn. Pearson, New York (2011)
Teh, C.K., Hamada, M., Fujita, T., Hara, H., Ikumi, N., Oowaki, Y.: Conditional data mapping flip-flops for low-power and high-performance systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(12), 1379–1383 (2006)
Chandrakasan, P., Sheng, S., Brodersen, R.W.: Low-power CMOS digital design. IEEE J. Solid-State Circuits 27, 473–484 (1992)
Alioto, M., Consoli, E., Palumbo, G.: General strategies to design nanometer flip-flops in the energy-delay space. IEEE Trans. Circuits Syst. I Regul. Pap. 57(7), 1583–1596 (2010)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this paper
Cite this paper
Manju, C.S., Poovizhi, N., Rajkumar, R. (2020). Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic. In: Hemanth, D.J., Kumar, V.D.A., Malathi, S., Castillo, O., Patrut, B. (eds) Emerging Trends in Computing and Expert Technology. COMET 2019. Lecture Notes on Data Engineering and Communications Technologies, vol 35. Springer, Cham. https://doi.org/10.1007/978-3-030-32150-5_5
Download citation
DOI: https://doi.org/10.1007/978-3-030-32150-5_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-32149-9
Online ISBN: 978-3-030-32150-5
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)