Abstract
IEEE SystemC is one of the most popular standards for system level design. With the Recoding Infrastructure for SystemC (RISC), a SystemC model can be executed at segment level in parallel. Although the parallel simulation is generally faster than its sequential counterpart, any data conflict among segments reduces the simulation speed significantly. In this paper, we propose for RISC users a coding guideline that increases the granularity of segments, so that the level of parallelism in the design increases and higher simulation speed becomes possible. Our experimental results show that a maximum speedup of over 6.0x is achieved on an 8-core processor, which is 1.7 times faster than parallel simulation without the coding guideline.
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Notes
- 1.
Note that the timing accuracy of a robust model will not be affected by extra delta cycles.
- 2.
The instance id is shown here, which is not of interest in this paper.
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Cheng, Z., Schmidt, T., Dömer, R. (2020). SystemC Coding Guideline for Faster Out-of-Order Parallel Discrete Event Simulation. In: Kazmierski, T., Steinhorst, S., Große, D. (eds) Languages, Design Methods, and Tools for Electronic System Design. Lecture Notes in Electrical Engineering, vol 611. Springer, Cham. https://doi.org/10.1007/978-3-030-31585-6_6
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DOI: https://doi.org/10.1007/978-3-030-31585-6_6
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