Abstract
We have seen several techniques to design the NoC-based multi-core systems in the previous chapters. To get confidence of the current operation of such system, it is required to test the manufactured chip. The task of manufacturing test of multi-core systems for its complete functionality is complex and time consuming (Kiamehr et al., Manufacturing threats. Springer, Berlin, 2018). Thus, the high stress to reduce time-to-market has made the test engineers to focus primarily onto the reduction of testtime, including thermal safety. A good test technique can improve the yield and reduce the testtime.
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Cheng, Y., Zhang, L., Han, Y., & Li, X. (2013). Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(2), 239–249.
Cplex (2013). www.ibm.com/software/in/integration/optimization/cplex.
Dubois, F., Sheibanyrad, A., Petrot, F., & Bahmani, M. (2013). Elevator-First: A deadlock-free distributed routing algorithm for vertically partially connected 3D-NoCs. IEEE Trans on Computers, 62(3), 609–615.
Huang, W., Ghosh, S., Velusamy, S., Sankaranarayanan, K., Skadron, K., & Stan, M. (2006). HotSpot: A compact thermal modeling methodology for early-stage VLSI design. IEEE Trans on Very Large Scale Integration (VLSI) Systems, 14(5), 501–513.
Iyengar, V., Chakrabarty, K., & Marinissen, E. J. (2002). Test wrapper and test access mechanism co-optimization for system-on-chip. Journal of Electronic Testing, 18(2), 213–230.
Kiamehr, S., Tahoori, M. B., & Anghel, L. (2018). Manufacturing threats. Springer, Berlin.
Liu, C., & Iyengar, V. (2006). Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE) (pp. 6–10).
Liu, C., Iyengar, V., & Pradhan, D. K. (2006). Thermal-aware testing of network-on-chip using multiple-frequency clocking. In Proceedings of VLSI Test Symposium (pp. 46–51).
Liu, C., Zhang, L., Han, Y., & Li, X. (2011a) Vertical interconnects squeezing in symmetric 3D mesh network-on-chip. In Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 357–362).
Manna, K., Mukherjee, P., Chattopadhyay, S., & Sengupta, I. (2018). Thermal-aware application mapping strategy for network-on-chip based system design. IEEE Transactions on Computers, 67(4), 528–542.
Manna, K., Reddy, C., Chattopadhyay, S., & Sengupta, I. (2015). Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation. International Journal of High Performance Systems Architecture (IJHPSA), 5(3), 141–152.
Marinissen, E., Iyengar, V., & Chakrabarty, K. (2002). A set of benchmarks for modular testing of socs. In Proceedings. International Test Conference (ITC) (pp. 519–528).
Segars, S. (1997). ARM7TDMI power consumption. IEEE Micro, 17(4), 12–19.
Sun, C., Chen, C. O., Kurian, G., Wei, L., Miller, J., Agarwal, A., et al. (2012). DSENT - A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip (pp. 201–210).
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Manna, K., Mathew, J. (2020). Thermal-Aware Test Strategies for NoC-Based Multi-Core Systems. In: Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures. Springer, Cham. https://doi.org/10.1007/978-3-030-31310-4_8
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DOI: https://doi.org/10.1007/978-3-030-31310-4_8
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