Abstract
In previous chapters, we have seen a number of application mapping algorithms together with TSV placement to minimize communication cost and energy consumption of NoC-based systems. However, algorithms which minimize communication cost (network latency) of the mapping may not consider thermal effects, resulting in hotspots and high peak temperatures, which in turn decrease the performance of systems, lifetime, reliability and leakage power dissipation. It may also create a very high-temperature variance within the chip, resulting in uneven delays across the chip.
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Manna, K., Mathew, J. (2020). Thermal-Aware Application Mapping Strategy for Designing a 2D NoC-Based Multi-Core Systems. In: Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures. Springer, Cham. https://doi.org/10.1007/978-3-030-31310-4_6
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