Abstract
In sophisticated embedded VLSI products, a single chip implementation integrating several Intellectual Property (IP) cores for performing various functions and possibly operating at different clock rates is quite common. This implementation is traditionally known as System-on-Chip (SoC). The SoC-based system design methodology focuses on the computational aspects of the problem. However, the number of components in a single chip and their performances continue to increase. To address complex real-life applications, it is required to have multiple processors which can cohesively communicate and provide high parallelism. This, in turn, has resulted in Chip Multi-Processing (CMP) systems to provide scalable computational power. Hundreds of processing cores are integrated on the SoC platform to build Multi-Processor System-on-Chip (MPSoC) in deep submicron (DSM) technology. In these systems, the design of communication architecture plays a major role in defining the area, performance and energy consumption of the overall system.
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Manna, K., Mathew, J. (2020). Introduction. In: Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures. Springer, Cham. https://doi.org/10.1007/978-3-030-31310-4_1
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