Skip to main content
SpringerLink
Log in

The Future of Security Validation and Verification

  • Chapter
  • First Online:
System-on-Chip Security

Abstract

Trustworthy System-on-Chip (SoC) design is vital to provide the hardware root-of-trust to enable a truly secure cyberspace. This book presented a wide variety of state-of-the-art SoC security validation and verification techniques for designing trustworthy SoCs. This chapter concludes the book with a summary of ideas presented in the previous chapters, and outlines the road map of future security validation challenges and opportunities.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 69.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 119.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. A. Ahmed, P. Mishra, QUEBS: qualifying event based search in concolic testing for validation of RTL models, in IEEE International Conference on Computer Design (ICCD) (2017), pp. 185–192

    Google Scholar 

  2. A. Ahmed, F. Farahmandi, Y. Iskander, P. Mishra, Scalable hardware Trojan activation by interleaving concrete simulation and symbolic execution, in IEEE International Test Conference (ITC) (2018)

    Google Scholar 

  3. A. Ahmed, F. Farahmandi, P. Mishra, Directed test generation using concolic testing of RTL models, in Design Automation and Test in Europe (DATE) (2018), pp. 1538–1543

    Google Scholar 

  4. K. Basu, P. Mishra, Efficient trace signal selection for post silicon validation and debug, in International Conference on VLSI Design (2011), pp. 352–357

    Google Scholar 

  5. K. Basu, P. Mishra, P. Patra, Observability-aware directed test generation for soft errors and crosstalk faults, in International Conference on VLSI Design (2013), pp. 291–296

    Google Scholar 

  6. S. Charles, Y. Lyu, P. Mishra, Real-time detection and localization of DoS attacks in NoC based SoCs, in Design Automation and Test in Europe (DATE) (2019)

    Google Scholar 

  7. M. Chen, P. Mishra, Functional test generation using efficient property clustering and learning techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3), 396–404 (2010)

    Article  Google Scholar 

  8. M. Chen, P. Mishra, Property learning techniques for efficient generation of directed tests. IEEE Trans. Comput. 60(6), 852–864 (2011)

    Article  MathSciNet  Google Scholar 

  9. M. Chen, P. Mishra, Assertion-based functional consistency checking between TLM and RTL models, in International Conference on VLSI Design (2013), pp. 320–325

    Google Scholar 

  10. M. Chen, P. Mishra, D. Kalita, Automatic RTL test generation from SystemC TLM specifications. ACM Trans. Embed. Comput. Syst. 11(2), article 38 (2012)

    Article  Google Scholar 

  11. M. Chen, X. Qin, P. Mishra, Learning-oriented property decomposition for automated generation of directed tests. J. Electr. Test. 30(3), 287–306 (2014)

    Article  Google Scholar 

  12. Common weakness enumeration (2017). https://cwe.mitre.org/

  13. J. Cruz, Y. Huang, P. Mishra, S. Bhunia, An automated configurable Trojan insertion framework for dynamic trust benchmarks, in Design Automation and Test in Europe (DATE), pp. 1598–1603 (2018)

    Google Scholar 

  14. J. Cruz, F. Farahmandi, A. Ahmed, P. Mishra, Hardware Trojan detection using ATPG and model checking, in International Conference on VLSI Design (2018), pp. 91–96

    Google Scholar 

  15. J. Cruz, P. Mishra, S. Bhunia, The metric matters: how to measure trust, in Design Automation Conference (DAC) (2019)

    Book  Google Scholar 

  16. DARPA system security integrated through hardware and firmware (SSITH) (2017). https://www.darpa.mil/program/system-security-integration-through-hardware-and-firmware

  17. F. Farahmandi, P. Mishra, Automated test generation for debugging arithmetic circuits, in Design Automation and Test in Europe (DATE), pp. 1351–1356 (2016)

    Google Scholar 

  18. F. Farahmandi, P. Mishra, FSM anomaly detection using formal analysis, in IEEE International Conference on Computer Design (ICCD) (2017), pp. 313–320

    Google Scholar 

  19. F. Farahmandi, P. Mishra, Automated test generation for debugging multiple bugs in arithmetic circuits. IEEE Trans. Comput. 68(2), 182–197 (2019)

    Article  MathSciNet  Google Scholar 

  20. F. Farahmandi, P. Mishra, S. Ray, Exploiting transaction level models for observability-aware post-silicon test generation, in Design Automation and Test in Europe (DATE) (2016), pp. 1477–1480

    Google Scholar 

  21. F. Farahmandi, Y. Huang, P. Mishra, Trojan localization using symbolic algebra, in Asia and South Pacific Design Automation Conference (ASPDAC) (2017), pp. 591–597

    Google Scholar 

  22. X. Guo, R.G. Dutta, Y. Jin, F. Farahmandi, P. Mishra, Pre-silicon security verification and validation: a formal perspective, in ACM/IEEE Design Automation Conference (DAC) (2015), pp. 145:1–145:6

    Google Scholar 

  23. X. Guo, R.G. Dutta, P. Mishra, Y. Jin, Scalable SoC trust verification using integrated theorem proving and model checking, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST) (2016), pp. 124–129

    Google Scholar 

  24. X. Guo, R.G. Dutta, P. Mishra, Y. Jin, Automatic code converter enhanced PCH framework for SoC trust verification. IEEE Trans. Very Large Scale Integr. Syst. 25(12), 3390–3400 (2017)

    Article  Google Scholar 

  25. Y. Huang, P. Mishra, Trace buffer attack on the AES cipher. J. Hardware Syst. Secur. 1(1), 68–84 (2017)

    Article  Google Scholar 

  26. Y. Huang, A. Chattopadhyay, P. Mishra, Trace buffer attack: Security versus observability study in post-silicon debug, in IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (2015), pp. 355–360

    Google Scholar 

  27. Y. Huang, S. Bhunia, P. Mishra, MERS: statistical test generation for side-channel analysis based Trojan detection, in ACM Conference on Computer and Communications Security (CCS) (2016), pp. 130–141

    Google Scholar 

  28. Y. Huang, S. Bhunia, P. Mishra, Scalable test generation for Trojan detection using side channel analysis. IEEE Trans. Inf. Forensics Secur. 13(11), 2746–2760 (2018)

    Article  Google Scholar 

  29. H.-M. Koo, P. Mishra, Functional test generation using design and property decomposition techniques. ACM Trans. Embed. Comput. Syst. 8(4), article 32 (2009)

    Article  Google Scholar 

  30. Y. Lyu, P. Mishra, A survey of side channel attacks on caches and countermeasures. J. Hardw. Syst. Secur. 2(2), 33–50 (2018)

    Article  Google Scholar 

  31. Y. Lyu, P. Mishra, Efficient test generation for Trojan detection using side channel analysis, in Design Automation and Test in Europe (DATE) (2019)

    Google Scholar 

  32. Y. Lyu, X. Qin, M. Chen, P. Mishra, Directed test generation for validation of cache coherence protocols, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (February 2018)

    Google Scholar 

  33. Y. Lyu, A. Ahmed, P. Mishra, Automated activation of multiple targets in RTL models using concolic testing, in Design Automation and Test in Europe (DATE) (2019)

    Google Scholar 

  34. P. Mishra, N. Dutt, Modeling and validation of pipeline specifications. ACM Trans. Embedded Comput. Syst. 3(1), 114–139 (2004)

    Article  Google Scholar 

  35. P. Mishra, N. Dutt, Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Des. Autom. Electr. Syst. 13(2), 36, article 42 (2008)

    Article  Google Scholar 

  36. P. Mishra, H. Tomiyama, A. Halambi, P. Grun, N. Dutt, A. Nicolau, Automatic modeling and validation of pipeline specifications driven by an architecture description language, in Asia and South Pacific Design Automation Conference (ASPDAC) and VLSI Design (2002), pp. 458–463

    Google Scholar 

  37. P. Mishra, R. Morad, A. Ziv, S. Ray, Post-silicon validation in the SoC era: a tutorial introduction, in IEEE Des. Test 34(3), 68–92 (2017)

    Google Scholar 

  38. A. Nahiyan, F. Farahmandi, P. Mishra, D. Forte, M. Tehranipoor, Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (May 2018)

    Google Scholar 

  39. A. Pouraghily, T. Wolf, R. Tessier, Hardware support for embedded operating system security, in International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2017), pp. 61–6

    Google Scholar 

  40. X. Qin, P. Mishra, Directed test generation for validation of multicore architectures. ACM Trans. Des. Autom. Electron. Syst. 17(3), article 24, 21 (2012)

    Article  Google Scholar 

  41. X. Qin, P. Mishra, Scalable test generation by interleaving concrete and symbolic execution, in International Conference on VLSI Design (2014), pp. 104–109

    Google Scholar 

  42. K. Rahmani, P. Mishra, Feature-based signal selection for post-silicon debug using machine learning, in IEEE Transactions on Emerging Topics in Computing (TETC) (December 2017)

    Google Scholar 

  43. K. Rahmani, S. Ray, P. Mishra, Post-silicon trace signal selection using machine learning techniques. IEEE Trans. Very Large Scale Integr. Syst. 25(2), 570–580 (2017)

    Article  Google Scholar 

  44. T. Thomas, A. Pouraghily, K. Hu, R. Tessier, T. Wolf, Multi-task support for security-enabled embedded processors, in International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2015), pp. 136–143

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. University of Florida, Gainesville, FL, USA

    Farimah Farahmandi & Prabhat Mishra

  2. Google, Mountain View, CA, USA

    Yuanwen Huang

Authors
  1. Farimah Farahmandi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yuanwen Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Prabhat Mishra
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Farahmandi, F., Huang, Y., Mishra, P. (2020). The Future of Security Validation and Verification. In: System-on-Chip Security. Springer, Cham. https://doi.org/10.1007/978-3-030-30596-3_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-30596-3_12

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-30595-6

  • Online ISBN: 978-3-030-30596-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation