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Efficient Cryptography on the RISC-V Architecture

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Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 11774))

Abstract

RISC-V is a promising free and open-source instruction set architecture. Most of the instruction set has been standardized and several hardware implementations are commercially available. In this paper we highlight features of RISC-V that are interesting for optimizing implementations of cryptographic primitives. We provide the first optimized assembly implementations of table-based AES, bitsliced AES, ChaCha, and the Keccak-\(f\)[1600] permutation for the RV32I instruction set. With respect to public-key cryptography, we study the performance of arbitrary-precision integer arithmetic without a carry flag. We then estimate the improvement that can be gained by several RISC-V extensions. These performance studies also serve to aid design choices for future RISC-V extensions and implementations.

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Notes

  1. 1.

    https://riscv.org/.

  2. 2.

    https://riscv.org/software-status.

  3. 3.

    https://www.sifive.com/boards/hifive1.

  4. 4.

    https://riscv.org/risc-v-cores.

  5. 5.

    https://github.com/XKCP/XKCP.

  6. 6.

    https://groups.google.com/forum/#!forum/riscv-xbitmanip.

  7. 7.

    https://github.com/riscv/riscv-bitmanip.

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Stoffelen, K. (2019). Efficient Cryptography on the RISC-V Architecture. In: Schwabe, P., Thériault, N. (eds) Progress in Cryptology – LATINCRYPT 2019. LATINCRYPT 2019. Lecture Notes in Computer Science(), vol 11774. Springer, Cham. https://doi.org/10.1007/978-3-030-30530-7_16

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  • DOI: https://doi.org/10.1007/978-3-030-30530-7_16

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