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A Power-Efficient Architecture for On-Chip Reservoir Computing

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Artificial Neural Networks and Machine Learning – ICANN 2019: Workshop and Special Sessions (ICANN 2019)

Abstract

Reservoir computing is a neuromorphic computing paradigm which is well suited for hardware implementations. In this work, an enhanced reservoir architecture is introduced as to lower the losses and improve mixing behaviour in silicon photonic reservoir computing designs.

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References

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Acknowledgements

This work was supported in part by the EU project PHRESCO H2020-ICT-2015-688579 and in part by the Research Foundation Flanders (FWO) under Grant 1S32818N.

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Correspondence to Stijn Sackesyn .

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Sackesyn, S., Ma, C., Katumba, A., Dambre, J., Bienstman, P. (2019). A Power-Efficient Architecture for On-Chip Reservoir Computing. In: Tetko, I., Kůrková, V., Karpov, P., Theis, F. (eds) Artificial Neural Networks and Machine Learning – ICANN 2019: Workshop and Special Sessions. ICANN 2019. Lecture Notes in Computer Science(), vol 11731. Springer, Cham. https://doi.org/10.1007/978-3-030-30493-5_16

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  • DOI: https://doi.org/10.1007/978-3-030-30493-5_16

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-30492-8

  • Online ISBN: 978-3-030-30493-5

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