Abstract
High Efficiency Video Coding (HEVC) doubles the coding efficiency of the prior Advanced Video Coding (AVC) standard but tackling its huge complexity calls for efficient HEVC codec implementations. The recent advances in Graphics Processing Units (GPUs) have made programmable general-purpose GPUs (GPGPUs) a popular option for accelerating various video coding tools. Massively parallel GPU architectures are particularly well suited for hardware-oriented full search (FS) algorithm in HEVC integer motion estimation (IME). This paper analyzes the feasibility of a GPU-accelerated FS implementation in the practical Kvazaar open-source HEVC encoder. According to our evaluations, implementing FS on AMD Radeon RX 480 GPU makes Kvazaar 12.5 times as fast as the respective anchor implemented entirely on an Intel 8-core i7 processor. However, the obtained speed gain is lost when fast IME algorithms are put into use in the anchor. For example, executing the anchor with hexagon-based search (HEXBS) algorithm is almost two times as fast as our GPU-accelerated proposal and the benefit of GPU offloading is reduced to a slight coding gain of 1.2%. Our results show that accelerating IME on a GPU speeds up non-practical encoders due to their enormous inherent complexity but the price paid with practical encoders tends to be too high. Conditional processing schemes of fast IME algorithms can be efficiently executed on processors without any substantial coding loss over that of FS. Nevertheless, we still believe there might be room for exploiting GPU on IME acceleration but GPU-parallelized fast algorithms are needed to get value for additional implementation cost and power budget.
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References
High Efficiency Video Coding, document ITU-T Rec. H.265 and ISO/IEC 23008-2 (HEVC), ITU-T and ISO/IEC, April 2013
Sullivan, G.J., Ohm, J.R., Han, W.J., Wiegand, T.: Overview of the High Efficiency Video Coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1649–1668 (2012)
Advanced Video Coding for Generic Audiovisual Services, document ITU-T Rec. H.264 and ISO/IEC 14496-10 (AVC), ITU-T and ISO/IEC, March 2009
Joint Collaborative Team on Video Coding Reference Software, ver. HM 16.0. http://hevc.hhi.fraunhofer.de/
x265. http://x265.org/
Kvazaar HEVC encoder. https://github.com/ultravideo/kvazaar
Lee, D., Oh, S.: Variable block size motion estimation implementation on compute unified device architecture (CUDA). In: Proceedings of the IEEE International Conference Consumer Electron., Las Vegas, NV, USA, January 2013
Lee, D., Sim, D., Cho, K., Oh, S.J.: Fast motion estimation for HEVC on graphics processing unit (GPU). J. Real-Time Image Proc. 12(2), 549–562 (2016)
Hojati, E., Franche, J., Coulombe, S., Vázquez, C.: Highly parallel HEVC motion estimation based on multiple temporal predictors and nested diamond search. In: Proceedings of the IEEE International Conference on Image Processing, Beijing, China (2017)
Wang, F., Zhou, D., Goto, S.: OpenCL based high-quality HEVC motion estimation on GPU. In: Proceedings of the IEEE International Conference on Image Processing, Paris, France (2014)
Wang, X., Song, L., Chen, M., Yang, J.: Paralleling variable block size motion estimation of HEVC on multi-core CPU plus GPU platform. In: Proceedings of the IEEE International Conference on Image Processing, Melbourne, Australia (2013)
Kao, H., Wang, I., Lee, C., Lo, C., Kang, H.: Accelerating HEVC motion estimation using GPU. In: Proceedings of the IEEE International Conference on Multimedia Big Data, Taipei, Taiwan (2016)
Takano, F., Igarashi, H., Moriyoshi, T.: 4K-UHD real-time HEVC encoder with GPU accelerated motion estimation. In: Proceedings of the IEEE International Conference on Image Processing, Beijing, China (2017)
Zhu, C., Lin, X., Chau, L.-P.: Hexagon-based search pattern for fast block motion estimation. IEEE Trans. Circuits Syst. Video Technol. 12(5), 349–355 (2002)
Werda, I., Chaouch, H., Samet, A., Ben Ayed, M.A., Masmoudi, N.: Optimal DSP based integer motion estimation implementation for H.264/AVC baseline encoder. Int. Arab J. Inform. Technol. 7(1), 96–107 (2010)
Bjøntegaard, G.: Calculation of average PSNR differences between RD-curves. Document VCEG-M33, Austin, Texas, USA (2001)
Bossen, F.: Common HM test conditions and software reference configurations. Document JCTVC-L1100. Switzerland, Geneva (2013)
Acknowledgements
This work was supported in part by the European Celtic-Plus project VIRTUOSE and the Academy of Finland (decision no. 301820). The authors would also like to thank all contributors of Kvazaar open-source project [6].
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Sainio, J., Mercat, A., Vanne, J. (2019). Hardware Deceleration of Kvazaar HEVC Encoder. In: Pnevmatikatos, D., Pelcat, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. Lecture Notes in Computer Science(), vol 11733. Springer, Cham. https://doi.org/10.1007/978-3-030-27562-4_22
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DOI: https://doi.org/10.1007/978-3-030-27562-4_22
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