Abstract
TCP/IP protocol stacks are usually complex protocols which require a high amount of computational power for the benefit of reliable communication. Therefore, a powerful and energy demanding processing core with an operating system is needed to achieve high data rates. In communication systems that are placed in a high temperature environment, e.g. electronics close to car engines or in aerospace applications, installation space is limited, temperatures of up to 175 \(^\circ \)C occur and a high energy consumption leads to further self-heating. Thus, a robust high temperature ASIC is mandatory in order to provide an energy efficient and small processing platform.
Special forms of the TCP/IP stack like Lightweight IP (lwIP) or Micro IP (uIP) are built for small or even embedded processors without the need of an operating system. In this work we implemented the lwIP and uIP stacks on the ARM Cortex-M0 and ARM Cortex-M3 processors and measured the throughput of the resulting System on Chips (SoC) designed for high temperature applications. The results show a relatively poor throughput of maximum 20.29 MBit/s even for the more powerful Cortex-M3 processor using the lwIP stack. Software and hardware improvements like a Direct Memory Access (DMA) mechanism and extended checksum hardware could increase the performance by 1250% resulting in 228 MBit/s.
As an exemplary target application, powerline communication in high temperature environment is chosen and a Design Space Exploration (DSE) was performed on the available physical parameters of a 180 nm SOI technology, capable of operating at 175 \(^\circ \)C. Results show that the best performing processor-software-combination is the Cortex-M0 which has a size of only 0.374 mm\({^2}\) and a power consumption of less than 1 mW at 10 MBit/s targeted throughput for the powerline application running the uIP stack. The increase in silicon area is only 9.7% and still this SoC is 2.57 times smaller and has 18.1 times less energy consumption compared to the Cortex-M3 baseline implementation.
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Notes
- 1.
The ASIC technology does not provide a dual-port memory capable of operating in a high temperature environment of up to 175 \(^\circ \)C.
- 2.
Measured using the binary code of the GCC cross compiler with optimization -O3.
References
Arm Limited: Arm 180 nm Ultra-Low-Power Platform. https://static.docs.arm.com/pfl0307/10/PIPD_Platform_TSMC_180ULL_BR_NC.pdf. Accessed 15 Jan 2019
Arm Limited: Arm Cortex-M Series Processors. https://developer.arm.com/products/processors/cortex-m. Accessed 23 Feb 2019
Arm Limited: Arm Cortex-M0 DesignStart Eval User Guide (2017)
Arm Limited: Arm Cortex-M3 DesignStart Eval RTL and FPGA Quick Start Guide (2017)
Vandana, B.: A theoretical study of low power Soi technology. IOSR J. VLSI Signal Process. 2, 30–37 (2013). https://doi.org/10.9790/4200-0253037
Bannatyne, R., Gifford, D., Klein, K., McCarville, K., Merritt, C., Neddermeyer, S.: Creation of an ARM\(\textregistered \) Cortex\(\textregistered \)-M0 microcontroller for high temperature embedded systems. In: Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT), pp. 31–35 (2017). https://doi.org/10.4071/2380-4491.2017.HiTEN.31
Chauvenet, C., Etheve, G., Sedjai, M., Sharma, M.: G3-PLC based IoT sensor networks for SmartGrid. In: 2017 IEEE International Symposium on Power Line Communications and its Applications (ISPLC), pp. 1–6, April 2017. https://doi.org/10.1109/ISPLC.2017.7897113
Dugan, J., Elliott, S., Mah, B.A., Poskanzer, J., Prabhu, K.: iPerf - the ultimate speed test tool for TCP, UDP and SCTP. https://iperf.fr/. Accessed 21 Feb 2019
Dunkels, A.: Design and implementation of the LwIP TCP/IP stack. Technical report, Swedish Institute of Computer Science, February 2001. https://doi.org/10.1145/1066116.1066118
Dunkels, A.: The uIP embedded TCP/IP stack - reference manual. Technical report, Swedish Institute of Computer Science, June 2006
Gouret, W., Nouvel, F., El-Zein, G.: Powerline communication on automotive network. In: 2007 IEEE 65th Vehicular Technology Conference - VTC2007-Spring, pp. 2545–2549, April 2007. https://doi.org/10.1109/VETECS.2007.524
Henriksson, T., Persson, N., Liu, D.: VLSI implementation of internet checksum calculation for 10 gigabit Ethernet. In: Proceedings of Design and Diganostics of Electronics, Cricuits and Systems, pp. 114–121 (2002)
HomePlug Powerline Alliance: HomePlug 1.0 Specification. Standard, HomePlug Power Alliance, CA, USA, December 2001
HomePlug Powerline Alliance: HomePlug AV2 Technology. Standard, HomePlug Power Alliance, CA, USA, Deember 2010
HomePlug Powerline Alliance: HomePlug Green PHY. Standard, HomePlug Power Alliance, CA, USA, July 2013
Hsiao, Y., Chen, M., Huang, K., Chu, Y., Yeh, C.: High speed UDP/IP ASIC design. In: 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 405–408, January 2009. https://doi.org/10.1109/ISPACS.2009.5383815
Jang, H., Chung, S.H., Yoo, D.H.: Design and implementation of a protocol offload engine for TCP/IP and remote direct memory access based onhardware/software coprocessing. Microprocess. Microsyst. 33(5–6), 333–342 (2009). https://doi.org/10.1016/j.micpro.2009.03.001
Jones, C.H.: Communications over aircraft power lines. In: 2006 IEEE International Symposium on Power Line Communications and Its Applications, pp. 149–154, March 2006. https://doi.org/10.1109/ISPLC.2006.247452
Langenbach, U., Berthe, A., Traskov, B., Weide, S., Hofmann, K., Gregorius, P.: A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform. In: 2013 IEEE Third International Conference on Consumer Electronics Berlin (ICCE-Berlin), pp. 381–384, September 2013. https://doi.org/10.1109/ICCE-Berlin.2013.6697997
Latchman, H.A., Katar, S., Yonge, L., Gavette, S.: Homeplug AV and IEEE 1901: A Handbook for PLC Designers and Users, 1st edn. Wiley-IEEE Press, Hoboken (2013)
Mahbub, H., Raj, J.: High Performance TCP/IP Networking. Pearson Prentice Hall, New Jersey (2004)
Mumtaz, S., Alsohaily, A., Pang, Z., Rayes, A., Tsang, K.F., Rodriguez, J.: Massive internet of things for industrial applications: addressing wireless iot connectivity challenges and ecosystem fragmentation. IEEE Ind. Electron. Mag. 11(1), 28–33 (2017). https://doi.org/10.1109/MIE.2016.2618724
Saunders, M.: Minimizing ARM Cortex CPU power by carefully considering and implementing combinations of these techniques, developers can realize substantial advantages. SILICON LABS, p. 1, September 2014
Sidler, D., István, Z., Alonso, G.: Low-latency TCP/IP stack for datacenter applications. In: 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–4, August 2016. https://doi.org/10.1109/FPL.2016.7577319
Sutter, G., Ruiz, M., López-Buedo, S., Alonso, G.: FPGA-based TCP/IP checksum offloading engine for 100 Gbps networks. 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–6 (2018)
Trevor, M.: The Designer’s Guide to the Cortex-M Processor Family - A Tutorial Approach. Elsevier, Oxford (2013)
Yiu, J.: The Definitive Guide to ARM Cortex-M0 and Cortex-M0+ Processors, 2nd edn. Newnes, Newton (2015)
Yiu, J.: ARM Cortex-M for beginners - an overview of the arm Cortex-M processor family and comparison. ARM White Paper, March 2017
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Stuckenberg, T., Gottschlich, M., Nolting, S., Blume, H. (2019). Design and Optimization of an ARM Cortex-M Based SoC for TCP/IP Communication in High Temperature Applications. In: Pnevmatikatos, D., Pelcat, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. Lecture Notes in Computer Science(), vol 11733. Springer, Cham. https://doi.org/10.1007/978-3-030-27562-4_12
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