Abstract
Heterogeneous architectures have become increasingly common. From co-packaging small and large cores, to GPUs alongside CPUs, to general-purpose heterogeneous-ISA architectures with cores implementing different ISAs. As diversity of execution cores grows, predictive models become of paramount importance for scheduling and resource allocation. In this paper, we investigate the capabilities of performance predictors in a heterogeneous-ISA setting, as well as the predictors’ effects on scheduler quality. We follow an unbiased feature selection methodology to identify the optimal set of features for this task, instead of pre-selecting features before training. Finally, we incorporate our findings in ML-based schedulers and evaluate their sensitivity to the underlying system’s level of heterogeneity. We show our schedulers to perform within 2–11% of an oracular scheduler across a variety of underlying heterogeneous-ISA multicore systems without modification.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Barbalace, A., Lyerly, R., Jelesnianski, C., Carno, A., Chuang, H.R., Ravindran, B.: Breaking the boundaries in heterogeneous-ISA datacenters. In: ASPLOS (2017)
Barbalace, A., et al.: Popcorn: bridging the programmability gap in heterogeneous-ISA platforms. In: ECCS, p. 29. ACM (2015)
Craeynest, K.V., Jaleel, A., Eeckhout, L., Narvaez, P., Emer, J.: Scheduling heterogeneous multi-cores through performance impact estimation (PIE). In: ISCA, pp. 213–224, June 2012. https://doi.org/10.1109/ISCA.2012.6237019
DeVuyst, M., Venkat, A., Tullsen, D.M.: Execution migration in a heterogeneous-ISA chip multiprocessor. In: ASPLOS XVII (2012)
Greenhalgh, P.: Big. LITTLE processing with arm cortex-A15 & cortex-A7. In: ARM White Paper, pp. 1–8 (2011)
Kahle, J.: The cell processor architecture. In: MICRO, p. 3. IEEE Computer Society (2005)
Kumar, R., Farkas, K.I., Jouppi, N.P., Ranganathan, P., Tullsen, D.M.: Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction. In: MICRO (2003)
Kumar, R., Tullsen, D.M., Ranganathan, P., Jouppi, N.P., Farkas, K.I.: Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In: ISCA (2004)
scikit learn: Scikit-learn python library. http://scikit-learn.org/stable/
Lim, K., Balkind, J., Wentzlaff, D.: Juxtapiton: enabling heterogeneous-ISA research with RISC-V and SPARC FPGA soft-cores. arXiv preprint arXiv:1811.08091 (2018)
Mittal, S., Vetter, J.S.: A survey of CPU-GPU heterogeneous computing techniques. ACM Comput. Surv. (CSUR) 47(4), 69 (2015)
Somu Muthukaruppan, T., Pathania, A., Mitra, T.: Price theory based power management for heterogeneous multi-cores. In: ASPLOS 2014. ACM (2014)
Torng, C., Wang, M., Batten, C.: Asymmetry-aware work-stealing runtimes. In: ISCA 2016 (2016). https://doi.org/10.1109/ISCA.2016.14
Variable, S.: A Multi-Core CPU Architecture for Low Power and High Performance. Whitepaper (2011). http://www.nvidia.com
Venkat, A., Basavaraj, H., Tullsen, D.M.: Composite-ISA cores: enabling multi-ISA heterogeneity using a single ISA. In: HPCA 2019 (2019)
Venkat, A., Shamasunder, S., Shacham, H., Tullsen, D.M.: HIPStR: heterogeneous-ISA program state relocation. In: ASLPOS (2016)
Venkat, A., Tullsen, D.M.: Harnessing ISA diversity: design of a heterogeneous-ISA chip multiprocessor. In: ISCA (2014)
Zheng, X., John, L.K., Gerstlauer, A.: Accurate phase-level cross-platform power and performance estimation. In: DAC (2016)
Acknowledgments
The authors would like to thank the anonymous reviewers for their helpful insights. This research was supported in part by NSF Grant CNS-1652925, NSF/Intel Foundational Microarchitecture Research Grant CCF-1823444, and a gift from Huawei.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Prodromou, A., Venkat, A., Tullsen, D.M. (2019). Platform-Agnostic Learning-Based Scheduling. In: Pnevmatikatos, D., Pelcat, M., Jung, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. Lecture Notes in Computer Science(), vol 11733. Springer, Cham. https://doi.org/10.1007/978-3-030-27562-4_10
Download citation
DOI: https://doi.org/10.1007/978-3-030-27562-4_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-27561-7
Online ISBN: 978-3-030-27562-4
eBook Packages: Computer ScienceComputer Science (R0)