Abstract
EM induced degradation of electric resistance in a variety of test structures is traditionally monitored by applying the DC stressing. A majority of proposed physical models describing the EM phenomenon have also assumed the DC load. At the same time all semiconductor integrated circuit (IC) chips operate with time-dependent, for example, AC or pulse, electric currents. Today’s multi/manycore microprocessors are working on different performance states and are the subject for dynamic power/thermal management schemes.
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Tan, S., Tahoori, M., Kim, T., Wang, S., Sun, Z., Kiamehr, S. (2019). Dynamic EM Models for Transient Stress Evolution and Recovery. In: Long-Term Reliability of Nanometer VLSI Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-26172-6_5
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