Abstract
To combat these runtime degradation issues manufacturers are currently adding guardband s to their designs, to ensure that the chips will be functional for a certain lifetime. However, this overdesign increases development and manufacturing costs, which is crucial for the embedded segment where low costs are a primary target. Hence, new approaches are necessary to take further advantage of scaled technology nodes. Therefore, a lot of research is done at various design levels. To name just a few, special NBTI-resilient circuits, input vector control , power gating , adaptive body biasing, dynamic voltage and frequency scaling (DVFS ), and enhanced instruction and application scheduling techniques are some of the existing aging mitigation methods. The last two techniques try to balance the necessary calculations on the available units (cores) to achieve equal wearout states on all units (cores), which should guarantee a longer lifetime of these parts.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
J. Abella, X. Vera, A. Gonzalez, Penelope: the NBTI-aware processor, in International Symposium on Microarchitecture (IEEE, Piscataway, 2007), pp. 85–96
ARM Limited, Cortex-A8 Technical Reference Manual (2010).
M. Basoglu, M. Orshansky, M. Erez, NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2010), pp. 253–258
D. Bild, G. Bok, R. Dick, Minimization of NBTI performance degradation using internal node control, in Proceedings of the Design, Automation and Test in Europe Conference (IEEE, Piscataway, 2009), pp. 148–153
N.L. Binkert, R.G. Dreslinski, L.R. Hsu, K.T. Lim, A.G. Saidi, S.K. Reinhardt, The M5 simulator: modeling networked systems. IEEE Micro 26(4), 52–60 (2006)
A. Calimera, E. Macii, M. Poncino, NBTI-aware power gating for concurrent leakage and aging optimization, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2009), pp. 127–132
T. Chan, J. Sartori, P. Gupta, R. Kumar, On the efficacy of NBTI mitigation techniques, in Proceedings of the Conference on Design, Automation and Test in Europe (IEEE, Piscataway, 2011), pp. 1–6
N. Choudhary, S. Wadhavkar, T. Shah, H. Mayukh, J. Gandhi, B. Dwiel, S. Navada, H. Najaf-abadi, E. Rotenberg, FabScalar: automating superscalar core design. IEEE Micro 32(3), 48–59 (2012)
F. Firouzi, S. Kiamehr, M.B. Tahoori, A linear programming approach for minimum NBTI vector selection, in Proceedings of the Great Lakes Symposium on VLSI (ACM, New York, 2011), pp. 253–258
F. Firouzi, S. Kiamehr, M.B. Tahoori, NBTI mitigation by NOP assignment and insertion, in Proceedings of the Conference on Design, Automation and Test in Europe (IEEE, Piscataway, 2012), pp. 218–223
J.L. Hennessy, D.A. Patterson, D. Goldberg, Computer Architecture: A Quantitative Approach (Morgan Kaufmann, Los Altos, 2003)
W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, M.R. Stan, HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. VLSI Syst. 14(5), 501–513 (2006)
R. Islam, A. Sabbavarapu, R. Patel, Power reduction schemes in next generation Intel atom processor based SoC for handheld applications, in IEEE Symposium on VLSI Circuits (IEEE, Piscataway, 2010), pp. 173–174
S. Kim, S.V. Kosonocky, D.R. Knebel, Understanding and minimizing ground bounce during mode transition of power gating structure, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2003), pp. 22–25
R. Kumar, G. Hinton, A family of 45 nm IA processors, in IEEE International Solid-State Circuits Conference on Digest of Technical Papers (IEEE, Piscataway, 2009), pp. 58 –59
S. Li, J.H. Ahn, R.D. Strong, J.B. Brockman, D.M. Tullsen, N.P. Jouppi, McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures, in Proceedings of the International Symposium on Microarchitecture (ACM, New York, 2009), pp. 469–480
miniMIPS, OpenCores: http://opencores.org/project,minimips [Online; accessed July 2012]
S. Naidu, E. Jacobs, Minimizing stand-by leakage power in static CMOS circuits, in Proceedings of Design, Automation and Test in Europe Conference (IEEE, Piscataway, 2001), pp. 370–376
F. Oboril, M. B. Tahoori, ExtraTime: modeling and analysis of wearout due to transistor aging at microarchitecture-level, in Proceedings of the International Conference on Dependable Systems and Networks (IEEE, Piscataway, 2012)
F. Oboril, M. B. Tahoori, Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation, in Proceedings of the European Test Symposium (IEEE, Piscataway, 2012)
F. Oboril, F. Firouzi, S. Kiamehr, M. Tahoori, Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions, in Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (IEEE, Piscataway, 2012), pp. 443–452
OpenRisc 1200, OpenCores: http://opencores.org/project,or1200_hp [Online; accessed July 2012]
T. Siddiqua, S. Gurumurthi, A multi-level approach to reduce the impact of NBTI on processor functional units, in Proceedings of the Great Lakes Symposium on VLSI (ACM, New York, 2010), pp. 67–72
A. Tiwari, J. Torrellas, Facelift: Hiding and slowing down aging in multicores, in Proceedings of the International Symposium on Microarchitecture (IEEE Computer Society, Washington, 2008), pp. 129–140
K. Usami, T. Shirai, T. Hashida, H. Masuda, S. Takeda, M. Nakata, N. Seki, H. Amano, M. Namiki, M. Imai, M. Kondo, H. Nakamura, Design and implementation of fine-grain power gating with ground bounce suppression, in International Conference on VLSI Design (IEEE, Piscataway, 2009), pp. 381–386
N.J. Wang, J. Quek, T.M. Rafacz, S.J. Patel, Characterizing the effects of transient faults on a high-performance processor pipeline, in Proceedings of the International Conference on Dependable Systems and Networks (IEEE Computer Society, Washington, 2004), pp. 61–71
Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, H. Yang, On the efficiency of input vector control to mitigate NBTI effects and leakage power, in Proceedings of the International Symposium on Quality of Electronic Design (IEEE Computer Society, Washington, 2009), pp. 19–26
W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, Y. Cao, The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans. VLSI Syst. 18(2), 173–183 (2010)
Y. Wang, X. Chen, W. Wang, Y. Cao, Y. Xie, H. Yang, Leakage power and circuit aging cooptimization by gate replacement techniques. IEEE Trans. Very Large Scale Integr. Syst. 99, 1–14 (2011)
L. Yuan, G. Qu, Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization, in Proceedings of the International Conference on Computer-Aided Design (IEEE, Piscataway, 2007), pp. 548–551
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Tan, S., Tahoori, M., Kim, T., Wang, S., Sun, Z., Kiamehr, S. (2019). Reducing Processor Wearout by Exploiting the Timing Slack of Instructions. In: Long-Term Reliability of Nanometer VLSI Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-26172-6_21
Download citation
DOI: https://doi.org/10.1007/978-3-030-26172-6_21
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-26171-9
Online ISBN: 978-3-030-26172-6
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)