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ExtraTime: Modeling and Analysis of Transistor Aging at Microarchitecture-Level

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Long-Term Reliability of Nanometer VLSI Systems

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Abstract

An aging-aware design of the entire processor, including the microarchitecture, is inevitable. To achieve this goal, it is necessary to assess transistor aging already in early design phases and to balance aging with other key design aspects (performance, power, and area). However, a major challenge is that detailed transistor-level information is not yet available in these phases making an accurate wearout estimation very difficult.

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Notes

  1. 1.

    Higher temperature, i.e., faster wearout, due to increased frequency is respected.

References

  1. J. Abella, X. Vera, A. Gonzalez, Penelope: the NBTI-aware processor, in International Symposium on Microarchitecture (IEEE, Piscataway, 2007), pp. 85–96

    Google Scholar 

  2. M. Agarwal, B.C. Paul, M. Zhang, S. Mitra, Circuit failure prediction and its application to transistor aging, in Proceedings of the VLSI Test Symposium (IEEE Computer Society, Silver Spring, 2007), pp. 277–286

    Google Scholar 

  3. M. Basoglu, M. Orshansky, M. Erez, NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2010), pp. 253–258

    Google Scholar 

  4. K. Bernstein, D.J. Frank, A.E. Gattiker, W. Haensch, B.L. Ji, S.R. Nassif, E.J. Nowak, D.J. Pearson, N.J. Rohrer, High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50, 433–449 (2006)

    Article  Google Scholar 

  5. N.L. Binkert, R.G. Dreslinski, L.R. Hsu, K.T. Lim, A.G. Saidi, S.K. Reinhardt, The M5 simulator: modeling networked systems. IEEE Micro 26(4), 52–60 (2006)

    Article  Google Scholar 

  6. K.A. Bowman, B.L. Austin, J.C. Eble, X. Tang, J.D. Meindl, A physical alpha-power law MOSFET model, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 1999), pp. 218–222

    Google Scholar 

  7. A. Calimera, E. Macii, M. Poncino, NBTI-aware power gating for concurrent leakage and aging optimization, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2009), pp. 127–132

    Google Scholar 

  8. T. Chan, J. Sartori, P. Gupta, R. Kumar, On the efficacy of NBTI mitigation techniques, in Proceedings of the Conference on Design, Automation and Test in Europe (IEEE, Piscataway, 2011), pp. 1–6

    Google Scholar 

  9. M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan, New-age: a negative bias temperature instability-estimation framework for microarchitectural components. Int. J. Parallel Program. 37, 417–431 (2009)

    Article  Google Scholar 

  10. D. Ernst, N. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, T. Mudge, Razor: a low-power pipeline based on circuit-level timing speculation, in Proceedings of the International Symposium on Microarchitecture (IEEE Computer Society, Washington, 2003), pp. 7–19

    Google Scholar 

  11. S. Feng, S. Gupta, S. Mahlke, Olay: combat the signs of aging with introspective reliability management. Ann Arbor 1001, 48109 (2008)

    Google Scholar 

  12. F. Firouzi, S. Kiamehr, M.B. Tahoori, A linear programming approach for minimum NBTI vector selection, in Proceedings of the Great Lakes Symposium on VLSI (ACM, New York, 2011), pp. 253–258

    Google Scholar 

  13. E. Gunadi, A.A. Sinkar, N.S. Kim, M.H. Lipasti, Combating aging with the colt duty cycle equalizer, in Proceedings of the International Symposium on Microarchitecture (IEEE Computer Society, Washington, 2010), pp. 103–114

    Google Scholar 

  14. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, M.R. Stan, HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. VLSI Syst. 14(5), 501–513 (2006)

    Article  Google Scholar 

  15. Intel, Intel 64 and IA-32 Architectures Software Developer’s Manual: Basic Architecture, vol. 1, 2006

    Google Scholar 

  16. R. Kalla, B. Sinharoy, W. Starke, M. Floyd, Power7: IBM’s next-generation server processor. IEEE Micro 30(2), 7–15 (2010)

    Article  Google Scholar 

  17. K. Kang, S.P. Park, K. Roy, M.A. Alam, Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance, in Proceedings of the International Conference on Computer-Aided Design (IEEE Press, New York, 2007), pp. 730–734

    Google Scholar 

  18. J. Keane, X. Wang, D. Persaud, C. Kim, An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB. IEEE J. Solid State Circuits 45(4), 817–829 (2010)

    Article  ADS  Google Scholar 

  19. R.E. Kessler, The Alpha 21264 microprocessor. IEEE Micro 19(2), 24–36 (1999)

    Article  Google Scholar 

  20. O. Khan, S. Kundu, A self-adaptive system architecture to address transistor aging, in Proceedings of the Conference on Design, Automation and Test in Europe (European Design and Automation Association, Leuven, 2009), pp. 81–86

    Google Scholar 

  21. S. Kim, S.V. Kosonocky, D.R. Knebel, Understanding and minimizing ground bounce during mode transition of power gating structure, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2003), pp. 22–25

    Google Scholar 

  22. R. Kumar, G. Hinton, A family of 45 nm IA processors, in IEEE International Solid-State Circuits Conference on Digest of Technical Papers (IEEE, Piscataway, 2009), pp. 58 –59

    Google Scholar 

  23. S. Li, J.H. Ahn, R.D. Strong, J.B. Brockman, D.M. Tullsen, N.P. Jouppi, McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures, in Proceedings of the International Symposium on Microarchitecture (ACM, New York, 2009), pp. 469–480

    Google Scholar 

  24. F. Oboril, M. B. Tahoori, Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation, in Proceedings of the European Test Symposium (IEEE, Piscataway, 2012)

    Google Scholar 

  25. F. Oboril, M.B. Tahoori, ExtraTime: modeling and analysis of wearout due to transistor aging at microarchitecture-level, in 2012 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) (IEEE, Piscataway, 2012), pp. 1–12

    Google Scholar 

  26. T. Siddiqua, S. Gurumurthi, A multi-level approach to reduce the impact of NBTI on processor functional units, in Proceedings of the Great Lakes Symposium on VLSI (ACM, New York, 2010), pp. 67–72

    Google Scholar 

  27. J. Srinivasan, S.V. Adve, P. Bose, J.A. Rivers, Lifetime reliability: Toward an architectural solution. IEEE Micro 25, 70–80 (2005)

    Article  Google Scholar 

  28. E. Takeda, Y. Nakagome, H. Kume, S. Asai, New hot-carrier injection and device degradation in submicron MOSFETs. IEEE Proc. I, Solid-State Electron Devices 130(3), 144–150 (1983)

    Article  Google Scholar 

  29. A. Tiwari, J. Torrellas, Facelift: Hiding and slowing down aging in multicores, in Proceedings of the International Symposium on Microarchitecture (IEEE Computer Society, Washington, 2008), pp. 129–140

    Google Scholar 

  30. V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, F. Baez, Reducing power in high-performance microprocessors, in Proceedings of the Design Automation Conference (ACM, New York, 1998), pp. 732–737

    Google Scholar 

  31. K. Usami, T. Shirai, T. Hashida, H. Masuda, S. Takeda, M. Nakata, N. Seki, H. Amano, M. Namiki, M. Imai, M. Kondo, H. Nakamura, Design and implementation of fine-grain power gating with ground bounce suppression, in International Conference on VLSI Design (IEEE, Piscataway, 2009), pp. 381–386

    Google Scholar 

  32. R. Vattikonda, W. Wang, Y. Cao, Modeling and minimization of PMOS NBTI effect for robust nanometer design, in Proceedings of the Design Automation Conference (ACM, New York, 2006), pp. 1047–1052

    Google Scholar 

  33. N.J. Wang, J. Quek, T.M. Rafacz, S.J. Patel, Characterizing the effects of transient faults on a high-performance processor pipeline, in Proceedings of the International Conference on Dependable Systems and Networks (IEEE Computer Society, Washington, 2004), pp. 61–71

    Google Scholar 

  34. Y. Wang, X. Chen, W. Wang, V. Balakrishnan, Y. Cao, Y. Xie, H. Yang, On the efficiency of input vector control to mitigate NBTI effects and leakage power, in Proceedings of the International Symposium on Quality of Electronic Design (IEEE Computer Society, Washington, 2009), pp. 19–26

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, University of California, Riverside, CA, USA

    Sheldon Tan

  2. Karlsruhe Institute of Technology, Karlsruhe, Germany

    Mehdi Tahoori & Shengcheng Wang

  3. Department of Electrical & Computer Engineering, University of California, Riverside, CA, USA

    Taeyoung Kim & Zeyu Sun

  4. Robert Bosch Starter Generator GmbH, Stuttgart, Germany

    Saman Kiamehr

Authors
  1. Sheldon Tan
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  2. Mehdi Tahoori
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  4. Shengcheng Wang
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  5. Zeyu Sun
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  6. Saman Kiamehr
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Tan, S., Tahoori, M., Kim, T., Wang, S., Sun, Z., Kiamehr, S. (2019). ExtraTime: Modeling and Analysis of Transistor Aging at Microarchitecture-Level. In: Long-Term Reliability of Nanometer VLSI Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-26172-6_20

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