Abstract
Unlike dynamic BTI which involves both stress and recovery periods, long periods of inactivity in parts of the circuit can result in static BTI (S-BTI ) stress. This phenomenon can accelerate the aging effect on circuit delay degradation. The delay degradation due to S-BTI stress of a few hours on logic circuits can be equivalent to D-BTI stress for 1 year. The critical point of operation of a circuit is when the circuit enters a dynamic phase after a long duration of static-stress phase. A worst-case timing analysis should be carried out considering this critical point of operation. Techniques have therefore been presented to consider this effect on clock-gated circuits.
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Tan, S., Tahoori, M., Kim, T., Wang, S., Sun, Z., Kiamehr, S. (2019). Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops. In: Long-Term Reliability of Nanometer VLSI Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-26172-6_18
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DOI: https://doi.org/10.1007/978-3-030-26172-6_18
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