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Efficiency and Loss Modeling of High-Vin Multi-MHz Converters

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Integrated High-Vin Multi-MHz Converters
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Abstract

In this chapter, a four-phase model for high-V in multi-MHz converters is described, which allows a separation of loss causes and loss locations. Non-linear parasitic capacitance, transition losses, dead time, and high-side supply generation have a major impact on the model accuracy. An improved model for both an asynchronous and a synchronous buck converter is proposed, which matches efficiency measurements by less than 3%. A preference for an asynchronous or a synchronous buck converter can be hardly distinguished as the achieved efficiency depends on the operating point, on the available switch technologies, and on the implementation of the high-side supply generation. A synchronous converter is superior in efficiency only if the dead time is precisely regulated to fully eliminate dead time related losses across varying operating points. A design indicator is proposed, which allows to benchmark an efficiency performance of converters independently of the operating point, which enables a comparison of state-of-the-art converters published at different operating points.

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References

  1. Basso C (2008) Switch-mode power supplies spice simulations and practical designs, 1st edn. McGraw-Hill, New York

    Google Scholar 

  2. Benda H, Spenke E (1967) Reverse recovery processes in silicon power rectifiers. Proc IEEE 55(8):1331–1354. https://doi.org/10.1109/PROC.1967.5834

    Article  Google Scholar 

  3. Chinag CY, Chen CL (2009) Zero-voltage-switching control for a PWM buck converter under DCM/CCM boundary. IEEE Trans Power Electron 24:2120–2126. https://doi.org/10.1109/TPEL.2009.2021186

    Article  Google Scholar 

  4. Eberle W, Zhang Z, Liu YF, Sen PC (2009) A practical switching loss model for buck voltage regulators. IEEE Trans Power Electron 24:700–713. https://doi.org/10.1109/TPEL.2008.2007845. http://ieeexplore.ieee.org/document/4757277/

    Article  Google Scholar 

  5. Graovac DD, Pürschel M, Kiep A (2006) MOSFET power losses calculation using the data-sheet parameters. Application note, Infineon, Automotive Power

    Google Scholar 

  6. Kelin J (2006) Synchronous buck MOSFET loss calculations with excel model. https://www.fairchildsemi.com/application-notes/AN/AN-6005.pdf

  7. Li CH, Lo YK, Chiu HJ, Chen TY (2012) Accurate power-loss estimation for continuous-current-conduction-mode synchronous buck converters. In: Anti-counterfeiting, security, and identification, pp 1–5. https://doi.org/10.1109/ICASID.2012.6325298. http://ieeexplore.ieee.org/document/6325298/

  8. Meade T, O’Sullivan D, Foley R, Achimescu C, Egan M, McCloskey P (2008) Parasitic inductance effect on switching losses for a high frequency DC-DC converter. In: 2008 Twenty-third annual IEEE applied power electronics conference and exposition, pp 3–9. https://doi.org/10.1109/APEC.2008.4522692. http://ieeexplore.ieee.org/document/4522692/

  9. Orabi M, Shawky A (2015) Proposed switching losses model for integrated point-of-load synchronous buck converters. IEEE Trans Power Electron 30:5136–5150. https://doi.org/10.1109/TPEL.2014.2363760. http://ieeexplore.ieee.org/document/6926802/

    Article  Google Scholar 

  10. Orabi M, Abou-Alfotouh A, Lotfi A (2008) Coss capacitance contribution to synchronous buck converter losses. In: 2008 IEEE power electronics specialists conference, pp 666–672. https://doi.org/10.1109/PESC.2008.4592006. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4592006

  11. Pam S, Sheehan R, Mukhopadhyay S (2012) Accurate loss model for DC-DC buck converter including non-linear driver output characteristics. In: 2012 Twenty-seventh annual IEEE applied power electronics conference and exposition (APEC), pp 721–726. https://doi.org/10.1109/APEC.2012.6165899. http://ieeexplore.ieee.org/document/6165899/

  12. Ren Y, Xu M, Zhou J, Lee FC (2005) Analytical loss model of power MOSFET. IEEE Trans Power Electron 21:310–319. https://doi.org/10.1109/TPEL.2005.869743. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1603662

    Article  Google Scholar 

  13. Vishay (revision 21-Jul-2017) Surface mount Schottky barrier rectifier. SS16 Datasheet, Document Number: 88746

    Google Scholar 

  14. Wang X, Huang AQ (2011) Capacitor energy variation based designer-side switching losses analysis for integrated synchronous buck converters in CMOS technology. https://doi.org/10.1109/APEC.2011.5744736. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5744736

  15. Wang X, Huang AQ (2011) Considerations on the optimal power stage segmentation algorithm for MHz integrated synchronous Buck DC-DC converters. https://doi.org/10.1109/ISPSD.2011.5890821. http://ieeexplore.ieee.org/document/5890821/

  16. Wang X, Park J, Brunt ERV, Huang AQ (2010) Switching losses analysis in MHz integrated synchronous buck converter to support optimal power stage width segmentation in CMOS technology. https://doi.org/10.1109/ECCE.2010.5618055. http://ieeexplore.ieee.org/document/5618055/

  17. Wang J, Chung HS, Li RT (2013) Characterization and experimental assessment of the effects of parasitic elements on the MOSFET switching performance. IEEE Trans Power Electron 28:573–590. https://doi.org/10.1109/TPEL.2012.2195332. http://ieeexplore.ieee.org/document/6192346/

    Article  Google Scholar 

  18. Wittmann J, Barner A, Rosahl T, Wicht B (2015) A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain. In: European solid-state circuits conference (ESSCIRC), ESSCIRC 2015 – 41st, pp 184–187. https://doi.org/10.1109/ESSCIRC.2015.7313859

  19. Wittmann J, Barner A, Rosahl T, Wicht B (2016) An 18V input 10MHz buck converter with 125ps mixed-signal dead time control. IEEE J Solid-State Circuits 51(7):1705–1715. https://doi.org/10.1109/JSSC.2016.2550498

    Article  Google Scholar 

  20. Yan W, Pi C, Li W, Liu R (2010) Dynamic dead-time controller for synchronous buck DC-DC converters. Electron Lett 46(2):164–165. https://doi.org/10.1049/el.2010.2651

    Article  Google Scholar 

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Appendix

Appendix

5.1.1 I Switch Conduction Losses

The total switch conduction losses P cond in buck converter are the sum of the conduction losses P cond,hs of the high-side switch and P cond,ls of the low-side switch.

Average losses over a power switch (conduction losses) in on-state during the on-time t on with an on-state resistance R on,hs of the high-side switch are calculated as

(5.19)

During the on-time of, e.g., the high-side switch, the inductor current is linearly rising from to (current ramp). In this time, the inductor current is

(5.20)

Inserting (5.20) into (5.19) and solving the integral results in

(5.21)

Expressing (5.21) by the output current by substituting leads to

(5.22)

As t on is vanishing in (5.21), the average power for a ramp current is independent of the ramp time. Consequently, the calculation of P cond,ls is accordingly for the falling current ramp from I Lmax to I Lmin during the on-time of the low-side switch, which is t off of the buck converter, with the on-state switch resistance R on,ls.

Thus, the total conduction losses are

(5.23)

Writing the equation in dependence of V in and V out by substituting the duty cycle results in

(5.24)

The first term of (5.24) shows that the losses of the high-side switches contribute with a factor of , while the losses of the low-side switch contribute with a factor of .

5.1.2 I Calculation of the DC Losses in the Inductor

The inductor DC losses P L,DC are calculated the same way as the switch conduction losses, as the inductor current ramps are also causing losses at the inductor DC resistance R dcr, instead of the switch on-state resistance. The average power loss P L,DC are thus calculated by modifying (5.23) (substitution of R on,hs and R on,ls) to

(5.25)

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Wittmann, J. (2020). Efficiency and Loss Modeling of High-Vin Multi-MHz Converters. In: Integrated High-Vin Multi-MHz Converters. Springer, Cham. https://doi.org/10.1007/978-3-030-25257-1_5

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  • DOI: https://doi.org/10.1007/978-3-030-25257-1_5

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