Disjoint Clustering in Combinatorial Circuits

Abstract

As the modern integrated circuit continues to grow in complexity, the design of very large-scale integrated (VLSI) circuits involves massive teams employing state-of-the-art computer-aided design (CAD) tools. An old, yet significant CAD problem for VLSI circuits is physical design automation. In this problem, one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface. The process of mapping an electronic design to a chip involves several physical design stages, one of which is clustering. Even for combinatorial circuits, there exists several models for the clustering problem. In particular, our primary consideration is the problem of disjoint clustering in combinatorial circuits for delay minimization (CN). The problem of clustering with replication for delay minimization has been well-studied and known to be solvable in polynomial time. However, replication can become expensive when it is unbounded. Consequently, CN is a problem worth investigating. We establish the computational complexities of several variants of CN. We also present a 2-approximation algorithm for an NP-hard variant of CN.

This research was supported in part by the Air Force Research Laboratory Information Directorate (AFRL/RI), through the Air Force Office of Scientific Research (AFOSR’s) Summer Faculty Fellowship Program, and the AFRL/RI Information Institute®, contract numbers FA9550-15-F-0001 and FA8750-16-3-6003.