Abstract
The collective fabrication of electronic devices let alone the rise within their speed has given an incredible success in the field of small and nano natural philosophy. Linear scaling of the device dimensions to a quasi-nano meter level permits the increase of a fancy system, integrated on a chip that drastically reduces their volume and power consumption per operate, while hugely increasing their speed. Currently, in superior processor technology, the physical gate length of a electronic transistor is getting into the sub-45 nm regime with a gate compound cadence than twenty seven. In analysis laboratories, transistors square measure being fictional which could be the prototypes of the last generation of CMOS devices supported the standard structures and materials. The proposed CMOS LECTOR 6T NAND gate gives the best performance than CMOS 4T NAND gate in term of power and speed from at the frequency [1 MHz to 100 MHz] respectively in cadence tool 45 nm technology.
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Acknowledgement
We acknowledge the CMR Group for its economic support in the form of CMRIT for the year 2018–19. We thank all the faculties in the Department of (ECE) Electronics and Communications Engineering and the lab staff for their support.
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Alluri, S., Rajendra Naik, B., Reddy, N.S.S., Venkata Ramanaiah, M. (2020). Performance Analysis of VLSI Circuits in 45 nm Technology. In: Satapathy, S.C., Raju, K.S., Shyamala, K., Krishna, D.R., Favorskaya, M.N. (eds) Advances in Decision Sciences, Image Processing, Security and Computer Vision. ICETE 2019. Learning and Analytics in Intelligent Systems, vol 4. Springer, Cham. https://doi.org/10.1007/978-3-030-24318-0_34
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