Abstract
This chapter starts with a brief review on the basic ageing phenomenon and the working principles and structures of MOSFET transistors. It then presents the unwanted but unavoidable oxide defects leading to charge traps and presents activation mechanisms. These defects can lead to a variety of known ageing effects, such as negative/positive bias instability, hot carrier degradation (alias hot carrier injection), random telegraph noise and time-dependent dielectric breakdown. The impact of these effects onto the individual transistor and consequentially the entire integrated circuit are then discussed. The remainder of this chapter reviews various quantitative ageing models. It starts with the fundamental explicit switching trap models, which individually describe each of the many traps inside every transistor oxide layer. The more abstract stochastic trap representation as capture-emission time maps is leading to practical models at the TCAD and electrical level, respectively. Based on these fundamental models, there are various further abstractions, bridging the gap between the nanosecond timescales, integrated circuits work at and the years or decades, over which circuit ageing is taking place. Analytic models offer a simple ageing assessment by making several worst-case assumptions, usually leading to a vast overestimation. CET map abstractions allow a realistic assessment of the ageing of small circuits such as individual critical paths. Finally, trap centric models enable several ways of accelerating ageing models. The most sophisticated ones can process millions of transistors over years of lifetime with a reasonable accuracy.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
\(3.16 \approx \sqrt {10}\), resulting in two equally spaced bins per factor 10 for logarithmic axes.
References
Alam, M. A. (2003). A critical examination of the mechanics of dynamic NBTI for PMOSFETs. In IEEE International Electron Device Meeting (pp. 345–348).
Barke, M. (2014). Aging aware robustness validation of digital integrated circuits. PhD thesis.
Bindu, B., Goes, G., Kaczer, B., & Grasser, T. (2009). Analytical solution of the switching trap model for negative bias temperature stress. In Integrated reliability works (pp. 93–96).
Cao, Y., Velamala, J., Sutaria, K., Chen, S. W., Ahlbin, J., Sanchez Esqueda, I., Bajura, M., & Fritze, M. (2014). Cross-layer modeling and simulation of circuit reliability. Transaction on Computer-Aided Design of Integrated Circuits and Systems, 33(1), 8–23.
Cho, M., Roussel, P., Kaczer, B., Degraeve, R., Franco, J., Aoulaiche, M. Chiarella, T., Kauerauf, T., Horiguchi, N., & Groeseneken, G. (2013). Channel hot carrier degradation mechanism in long/short channel n-FinFETs. IEEE Transaction on Electron Devices, 60(12), 4002–4007.
Choudhury, M., Chandra, V., Mohanram, K., & Aitken, R. (2010). Analytical model for TDDB-based performance degradation in combinational logic. In Proceedings – Design, Automation and Test in Europe (DATE) (pp. 423–428).
DeBole, M., Ramakrishnan, K., Balakrishnan, V., Wang, W., Luo, H., Wang, Y., Xie, Y., Cao, Y., & Vijaykrishnan, N. (2009). A framework for estimating NBTI degradation of microarchitectural components. In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC) (pp. 455–460).
Degraeve, R., Groeseneken, G., Bellens, R., Ogier, J. L., Depas, M., Roussel, P. J., & Maes, H. E. (1998). New insights in the relation between electron trap generation and the statistical properties of oxide breakdown. IEEE Transactions on Electron Devices, 45(4), 904–911.
Eilers, R. (2017). Abstraction of aging models for high level degradation prediction. PhD thesis.
Eilers, R., Metzdorf, M., Helms, D., & Nebel, W. (2014). Efficient NBTI modeling technique considering recovery effects. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED) (pp. 177–182).
Giering, K. U., Sohrmann, C., Rzepa, G., Heiß, L., Grasser, T., & Jancke, R. (2014). NBTI modeling in analog circuits and its application to long-term aging simulations. In Proceeding of International Integrated Reliability Workshop (IIRW) (pp. 29–34).
Giering, K. U., Rott, G., Rzepa, G., Reisinger, H., Puppala, A. K., Reich, T., Gustin, W., Grasser, T., & Jancke, R. (2014). Analog-circuit NBTI degradation and time-dependent NBTI variability. In Proceeding of International Reliability Physics Symposium (IRPS).
Grasser, T. (2014). Bias temperature instability for devices and circuits. New York: Springer. ISBN 978-1-4614-7909-3.
Grasser, T., Kaczer, B., Goes, W., Aichinger, T., Hehenberger, P., & Nelhiebel, M. (2009). A two-stage model for negative bias temperature instability. In Proceeding of International Reliability Physics Symposium (IRPS).
Grasser, T., Reisinger, H., Wagner, P.-J., Schanovsky, F., Goes, W., & Kaczer, B. (2010). The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability. In Proceeding of International Reliability Physics Symposium (IRPS) (pp. 16–25).
Grasser, T., Kaczer, B., Goes, W., Reisinger, H., Aichinger, T. Hehenberger, P., Wagner, P. J., Schanovsky, F., Franco, J., Toledano Luque, M., & Nelhiebel, M. (2011). The paradigm shift in understanding the bias temperature instability: From reaction–diffusion to switching oxide traps. IEEE Transaction on Electron Devices, 58, 3652–3666.
Grasser, T., Rott, K., Reisinger, H., Waltl, M., Schanovsky, F., & Kaczer, B. (2014). NBTI in nanoscale MOSFETs—The ultimate modeling benchmark. IEEE Transaction on Electron Devices, 61(11), 3586–3593.
Helms, D. (2009). Leakage models for high level power estimation. PhD thesis.
Helms, D., Schmidt, E., & Nebel, W. (2004). Leakage in CMOS circuits – An introduction. In Proceeding of PATMOS (pp. 17–35).
Huard, V., Parthasarathy, C., Guerin, C., & Denais, M. (2006). Physical modeling of negative bias temperature instabilities for predictive extrapolation. In IEEE International Reliability Physics Symposium Proceedings (IRPS).
Huard, V., Pion, E., Cacho, F., Croain, D., Robert, V., Delater, R., Mergault, P., Engels, S. Flatresse, P., Amador, R., & Anghel, L. (2012). A predictive bottom-up hierarchical approach to digital system reliability. In Proceeding of IEEE International Reliability Physics Symposium (IRPS)
Illarionov, Y., Smith, A., Vaziri, S., Ostling, M., Mueller, T., Lemme, M., & Grasser, T. (2015). Hot-carrier degradation and bias-temperature instability in single-layer graphene field-effect transistors: Similarities and differences. IEEE Transaction on Electron Devices, 62(11), 3876–3881.
Jeppson, K. O., & Svensson, C. M. (1977). Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices. Journal of Applied Physics, 48, 2004–2014
Kaczer, B., Mahato, S., de Almeida Camargo, V., Toledano-Luque, M., Roussel, P. J., Grasser, T., Catthoor, F., Dobrovolny, P., Zuber, P., Wirth G., & Groeseneken, G. (2011). Atomistic approach to variability of bias-temperature instability in circuit simulations. In Proceeding of IEEE International Reliability Physics Symposium (IRPS).
Kaczer, B., Franco, J., Weckx, P., Roussel, P. J., Putcha, V., Bury, E., Simicic, M., Chasin, A., Linten, D., Parvais, B., Catthoor, F., Rzepa, G., Waltl, M., & Grasser, T. (2018). A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability. Microelectronics Reliability, 81, 186–194.
Lienig, J. (2006). Introduction to electromigration-aware physical design. In Proceeding of Electromigration-Aware Physical Design (ISPD) (39–46).
Lorenz, D. (2012). Aging analysis of digital integrated circuits. PhD thesis.
Lorenz, D., Barke, M., & Schlichtmann, U. (2010). Aging analysis at gate and macro cell level. In Proceeding of EEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD).
Mahapatra, S., Ahmed, K., Varghese, D., Islam, A. E., Gupta, G., Madhav, L., Saha, D., & Alam, M. A. (2007). On the physical mechanism of NBTI in silicon oxynitride p-MOSFETs: Can differences in insulator processing conditions resolve the interface trap generation versus hole trapping controversy? In Proceeding of IEEE International Reliability Physics Symposium (IRPS) (pp. 1–9).
Mahapatra, S., Goel, N., Desai, S., Gupta, S., Jose, B., Mukhopadhyay, S., Joshi, K., Jain, A., Islam, A. E., & Alam, M. A. (2013). A comparative study of different physics-based NBTI models. IEEE Transactions on Electron Devices, 60, 901–916.
Metzdorf, M. (2018). Integration einer Zuverlässigkeitsbewertung und -optimierung in den RT- und Gate-Level Entwurfsfluss. PhD Thesis.
Mintarno, E., Chandra, V., Pietromonaco, D., Aitken, R., & Dutton, R. W. (2013). Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor. In Proceeding of IEEE International Reliability Physics Symposium (IRPS).
Mukhopadhyay, S., & Mahapatra, S. (2015). An experimental perspective of trap generation under BTI stress. IEEE Transactions on Electron Devices, 62(7), 2092–2097.
Paydavosi, N., Morshed, T. H., Lu, D. D., Yang, W., Dunga, M. V., Xi, X., He, J., Liu, W., Cao, K. M., Jin, X., Ou, J. J., Chan, M., Niknejad, A. M., & Hu, C. (2013). BSIM4v4.8.0 MOSFET model – User’s manual.
Reisinger, H., Blank, O., Heinrigs, W., Mühlhoff, A., Gustin, W., & Schlünder, C. (2006). Analysis of NBTI degradation- and recovery-behavior based on ultra fast Vth-measurements. In Proceeding of IEEE International Reliability Physics Symposium (IRPS) (pp. 448–453).
Reisinger, H., Grasser, T., Gustin, W., & Schlünder, C. (2010). The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress. In Proceeding of IEEE International Reliability Physics Symposium (IRPS).
Rott, G. A., Rott, K., Reisinger, H., Gustin, W., & Grasser, T. (2014). Mixture of negative bias temperature instability and hot-carrier driven threshold voltage degradation of 130 nm technology p-channel transistors. Microelectronics Reliability, 54(9), 2310–2314.
Rzepa, G. (2013). Microscopic modeling of NBTI in MOS transistors, MA thesis.
Sarkar, D., Xie, X., Liu, W., Cao, W., Kang, J., Gong, Y., Kraemer, S., Ajayan, P. M., & Banerjee, K. (2015). A subthermionic tunnel field-effect transistor with an atomically thin channel. Nature, 526, 91–95.
Tam, S., Ko, P. K., & Hu, C. (1984). Lucky-electron model of channel hot-electron injection in MOSFET’s. IEEE Transactions on Electron Devices, 31(9), 1116–1125.
Tsunomura, T., Nishimura, J. I., Kumar, A., Nishida, A., Inaba, S., Takeuchi, K., Hiramoto, T., & Mogami, T. (2011). Suppression of VT variability degradation induced by NBTI with RDF control. In Symposium on VLSI Technology (pp. 150–151).
Tyaginov, S. E., Starkov, I. A., Enichlmair, H., Park, J. M., Jungemann, C., & Grasser, T. (2011). Physics-based hot-carrier degradation models. Electrochemical Society Transactions, 35(4), 321–352.
Tyaginov, S. E., Makarov, A. A., Jech, M., Vexler, M. I., Franco, J., Kaczer, B., & Grasser, T. (2018). Physical principles of self-consistent simulation of the generation of interface states and the transport of hot charge carriers in field-effect transistors based on metal–oxide–semiconductor structures. Physics of Semiconductor Devices, 52, 254–259.
Unutulmaz, A., Helms, D., Eilers, R., Metzdorf, M., Kaczer, B., & Nebel, W. (2016). Analysis of NBTI effects on high frequency digital circuits. In Proceeding of Design, Automation & Test in Europe Conference & Exhibition (DATE).
van der Wel, A. P., Klumperink, E., Kolhatkar, J., Eric Hoekstra, E., Snoeij, M., Salm, C., Wallinga, H., & Nauta, B. (2007). Low-frequency noise phenomena in switched MOSFETs. IEEE Journal of Solid-State Circuits, 42(3), 540–550.
Wang, W., Yang, S., Bhardwaj, S., Vattikonda, R., Vrudhula, S., Liu, F., & Cao, Y. (2007). The Impact of NBTI on the Performance of Combinational and Sequential Circuits. In Proceeding of Design Automation Conference (DAC) (pp. 364–369)
Wimmer, Y., El-Sayed, A.-M., Gös, W., Grasser, T., & Shluger, A. L. (2016). Role of hydrogen in volatile behaviour of defects in SiO 2-based electronic devices. Proceedings of the Royal Society A, 472, 2190.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Helms, D. (2020). Understanding Ageing Mechanisms. In: Halak, B. (eds) Ageing of Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-23781-3_1
Download citation
DOI: https://doi.org/10.1007/978-3-030-23781-3_1
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-23780-6
Online ISBN: 978-3-030-23781-3
eBook Packages: EngineeringEngineering (R0)