SOC Physical Design Verification

Abstract

This chapter deals with the physical design verification of a system on chip, which are logic equivalence check and STA analysis flow carried out at every stage of the physical design of a SOC. The chapter explains electrical rules checks (ERC), verification of interconnect effects, like cross talk, IR analysis, and the antenna effects. It also deals with design rule checks (DRC) and design for manufacturing (DRM) rules check for the SOC design before the design tape-out to the fabrication house.