Abstract
This paper proposes a switched-current (SI) sampled and hold circuit (SH) for the 2+2 multi-stage noise shaping (MASH) delta-sigma (ƩΔ) modulator, which is fabricated in TSMC 0.18 μm 1P6 M CMOS process. In the proposed design, the input impedance can be reduced by a factor of (1+A) using the modified feedback memory cell to obtain low transmission error and the circuit stability can be improved with the cross-connected common-mode feedforward circuit (CMFF). A differential cross-connected CMFF circuit can speed up a fast-response circuit and bring a stabilized output current. The proposed digital noise-cancellation circuit not only eliminates the higher-order quantisation noise from the last stage but also cancels the lower-order quantisation noise from the earlier stage of the modulator. The simulation results show that the signal-to-noise and distortion ratio (SNDR) is approximately 87.1 dB, and the effective number of bits (ENOBs) is roughly 14.18 bits at a sampling rate of 10.24 MHz with an oversampling ratio (OSR) of 256 and a signal bandwidth of 20 kHz. The designed chip draws 18.19 mW from the supply voltage of 1.8 V and occupies a core area of 0.13 mm2.
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Sung, GM., Gunnam, L.C., Sung, SH. (2019). Switched-Current Sampled and Hold Circuit with Digital Noise Cancellation Circuit for 2+2 MASH ƩΔ Modulator. In: Arai, K., Bhatia, R., Kapoor, S. (eds) Intelligent Computing. CompCom 2019. Advances in Intelligent Systems and Computing, vol 998. Springer, Cham. https://doi.org/10.1007/978-3-030-22868-2_30
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DOI: https://doi.org/10.1007/978-3-030-22868-2_30
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