Skip to main content

SOI FinFET for Computer Networks and Cyber Security Systems

  • Chapter
  • First Online:
Handbook of Computer Networks and Cyber Security

Abstract

Today, computer-based systems have become common in everyday life and these systems are used to store leverage information and people are more willing to communicate this sensitive information with the real world. So, computer networks have become the emerging domain for connecting physical devices like home appliances, vehicles, and other embedded electronics, software, actuators, and sensor-based systems, and security of these systems from cyberattacks is essential for secure communication. This results in the easy and safe communication between different entities. So, modern advanced computer systems with efficient integrated transistor technology provide the security and privacy to the computer-based real world. This chapter explores the advanced Silicon-on Insulator Fin Field EffectTransistor (SOI FinFET) technology which is the basic unit of integrated circuit used in every electronic gadget and computer hardware. In this chapter, performance analysis of device-D1 (high-k SOI FinFET structure) is done to implement the efficient computer hardware over a wide temperature range (200–450 K). The attempt is done to find out the ZTC (zero temperature coefficient) biased point of SOI FinFET device to have stable, reliable, and secure systems. The proposed device analysis will provide the hardware design flexibility in the electronic circuits, microprocessors, computer hardware, and thermally stable interfacing components for security applications of information technology.

The potential parameters of device-D1 like AV (intrinsic gain), gm (transconductance), VEA (early voltage), gd (output conductance), Ioff (off current), Ion (on current), Ion/Ioff ratio, Cgs (gate-source capacitance), Cgd (gate-drain capacitance), fT (cutoff frequency), and SS (subthreshold slope) are subjected to analysis to evaluate the performance over wide temperature environment. The validation of temperature-based performance of device-D1 gives an opportunity to design numerous analog/RF and digital components in Internet cyber security infrastructure environments.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 219.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 299.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Hisamoto, D., Lee, W. C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., et al. (2000). FinFET-A self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47, 2320–2325.

    Article  Google Scholar 

  2. Gupta, B., Agrawal, D. P., & Yamaguchi, S. (2016). Handbook of research on modern cryptographic solutions for computer and cyber security. Hershey, PA: IGI Global.

    Book  Google Scholar 

  3. Ab Malek, M. S. B., Ahmadon, M. A. B., Yamaguchi, S., & Gupta, B. B. (2016). On privacy verification in the IoT service based on PN 2. In Consumer Electronics 2016 IEEE 5th Global Conference, IEEE (pp. 1–4).

    Google Scholar 

  4. Memos, V. A., Psannis, K. E., Ishibashi, Y., Kim, B.-G., & Gupta, B. B. (2017). An efficient algorithm for media-based surveillance system (EAMSuS) in IoT Smart City framework. Future Generation Computer Systems, 83, 619–628.

    Article  Google Scholar 

  5. Tewari, A., & Gupta, B. B. (2017). Cryptanalysis of a novel ultra-lightweight mutual authentication protocol for IoT devices using RFID tags. Journal of Supercomputing, 73, 1085–1102.

    Article  Google Scholar 

  6. Chang, V., Kuo, Y.-H., & Ramachandran, M. (2016). Cloud computing adoption framework: A security framework for business clouds. Future Generation Computer Systems, 57, 24–41.

    Article  Google Scholar 

  7. Pal, P. K., Kaushik, B. K., & Dasgupta, S. (2013). High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs. IEEE Transactions on Electron Devices, 60, 3371–3377.

    Article  Google Scholar 

  8. Pal, P. K., Kaushik, B. K., & Dasgupta, S. (2014). Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective. IEEE Transactions on Electron Devices, 61, 3579–3585.

    Article  Google Scholar 

  9. Kumar, S., & Raj, B. (2016). Simulations and modeling of TFET for low power design (Handbook of research on computational simulation and modeling in engineering) (pp. 640–667). Hershey, PA: IGI Global.

    Google Scholar 

  10. Nowak, E. J., Aller, I., Ludwig, T., Kim, K., Joshi, R. V., Chuang, C.-T., et al. (2004). Turning silicon on its edge [double gate CMOS/FinFET technology]. IEEE Circuits and Devices Magazine, 20, 20–31.

    Article  Google Scholar 

  11. Kranti, A., & Armstrong, G. A. (2007). Source/drain extension region engineering in FinFETs for low-voltage analog applications. IEEE Electron Device Letters, 28, 139–141.

    Article  Google Scholar 

  12. Virani, H. G., Adari, R. B. R., & Kottantharayil, A. (2010). Dual-k spacer device architecture for the improvement of performance of silicon n-channel tunnel FETs. IEEE Transactions on Electron Devices, 57, 2410–2417.

    Article  Google Scholar 

  13. Kumar, S., & Raj, B. (2015). Compact channel potential analytical modeling of DG-TFET based on evanescent-mode approach. Journal of Computational Electronics, 14, 820–827.

    Article  Google Scholar 

  14. Patil, G. C., & Qureshi, S. (2012). Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits. Semiconductor Science and Technology, 27, 045004.

    Article  Google Scholar 

  15. Nandi, A., Saxena, A. K., & Dasgupta, S. (2012). Impact of dual-k spacer on analog performance of underlap FinFET. Microelectronics Journal, 43, 883–887.

    Article  Google Scholar 

  16. Pal, P. K., Kaushik, B. K., & Dasgupta, S. (2015). Asymmetric dual-spacer trigate FinFET device-circuit codesign and its variability analysis. IEEE Transactions on Electron Devices, 62, 1105–1112.

    Article  Google Scholar 

  17. Jain, N., & Raj, B. (2016). An analog and digital design perspective comprehensive approach on Fin-FET (fin-field effect transistor) technology—A review. Reviews in Advanced Sciences and Engineering, 5, 123–137.

    Article  Google Scholar 

  18. Goel, A., Gupta, S. K., & Roy, K. (2011). Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Transactions on Electron Devices, 58, 296–308.

    Article  Google Scholar 

  19. Kumar, S., & Raj, B. (2016). Analysis of I ON and Ambipolar current for dual-material gate-drain overlapped DG-TFET. Journal of Nanoelectronics and Optoelectronics, 11, 323–333.

    Article  Google Scholar 

  20. Atzori, L., Iera, A., & Morabito, G. (2010). The internet of things: A survey. Computer Networks, 54, 2787–2805.

    Article  MATH  Google Scholar 

  21. Mohanty, S. P. (2015). Nanoelectronic mixed-signal system design. New York: McGraw-Hill Education.

    Google Scholar 

  22. Jain, A., Sharma, S., & Raj, B. (2016). Design and analysis of high sensitivity photosensor using cylindrical surrounding gate MOSFET for low power sensor applications. Engineering Science and Technology, 19, 1864–1870.

    Google Scholar 

  23. Kumar, S., & Raj, B. Simulation of nanoscale TFET device structure for low power applications. In Proceedings of International Conference on Electrical Electronics and Industrial Automation held on 23rd--24th January 2016. Pattaya, Thailand. ISBN: 9788193137338.

    Google Scholar 

  24. Kumar, S., Kumar, S., Karamveer, Kumar, K., & Raj, B. (2016). Analysis of double gate dual material TFET device for low power SRAM cell design. Quantum Matter, 5, 762–766.

    Article  Google Scholar 

  25. Adat, V., & Gupta, B. B. (2018). Security in internet of things: Issues, challenges, taxonomy, and architecture. Telecommunication Systems, 67, 423–441.

    Article  Google Scholar 

  26. Stergiou, C., Psannis, K. E., Kim, B.-G., & Gupta, B. (2018). Secure integration of IoT and cloud computing. Future Generation Computer Systems, 78, 964–975.

    Article  Google Scholar 

  27. Jain, N., & Raj, B. (2018). Capacitance/resistance modeling and analog performance evaluation of 3-D SOI FinFET structure for circuit perspective applications. World Scientific News, 113, 194–209.

    Google Scholar 

  28. Kumar, S., & Raj, B. (2015). Modeling of DG-tunnel FET for low power VLSI circuit design. In 2015 Eighth International Conference on Contemporary Computing, IEEE (pp. 455–458).

    Google Scholar 

  29. Gupta, B. B. (2018). Computer and cyber security: Principles, algorithm, applications, and perspectives. Boca Raton, FL: CRC Press.

    Google Scholar 

  30. Ko, H., Mesicek, L., Choi, J., Choi, J., & Hwang, S. (2018). A study on secure contents strategies for applications with DRM on cloud computing. International Journal of Cloud Applications and Computing, 8, 143–153.

    Article  Google Scholar 

  31. Wang, L., Li, L., Li, J., Li, J., Gupta, B. B., & Liu, X. (2019). Compressive sensing of medical images with confidentially homomorphic aggregations. IEEE Internet Things Journal, 6, 1402–1409.

    Article  Google Scholar 

  32. Mohapatra, S. K., Pradhan, K. P., & Sahu, P. K. (2015). Temperature dependence inflection point in ultra-thin Si directly on insulator (SDOI) MOSFETs: An influence to key performance metrics. Superlattices and Microstructures, 78, 134–143.

    Article  Google Scholar 

  33. Singh, S., Raj, B., & Vishvakarma, S. K. (2018). Analytical modeling of split-gate junction-less transistor for a biosensor application. Sensing and Bio-Sensing Research, 18, 31–36.

    Article  Google Scholar 

  34. Sahu, P. K., Mohapatra, S. K., & Pradhan, K. P. (2015). Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges. Materials Science in Semiconductor Processing, 31, 175–183.

    Article  Google Scholar 

  35. Magnone, P., Mercha, A., Subramanian, V., Parvais, P., Collaert, N., Dehan, M., et al. (2009). Matching performance of FinFET devices with fin widths down to 10 nm. IEEE Electron Device Letters, 30, 1374.

    Article  Google Scholar 

  36. Sharma, S. K., Raj, B., & Khosla, M. (2016). A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects. Microelectronics Journal, 53, 65–72.

    Article  Google Scholar 

  37. Pradhan, K. P., Sahu, P. K., & Mohapatra, S. K. (2015). Analysis of symmetric high-k spacer (SHS) trigate wavy FinFET: A novel device. In India Conference (INDICON), 2015 Annual IEEE, IEEE (pp. 1–3).

    Google Scholar 

  38. Nowak, E. J. (2002). Maintaining the benefits of CMOS scaling when scaling bogs down. IBM Journal of Research and Development, 46, 169–180.

    Article  Google Scholar 

  39. Trivedi, V., Fossum, J. G., & Chowdhury, M. M. (2005). Nanoscale FinFETs with gate-source/drain underlap. IEEE Transactions on Electron Devices, 52, 56–62.

    Article  Google Scholar 

  40. Koley, K., Dutta, A., Syamal, B., Saha, S. K., & Sarkar, C. K. (2013). Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications. IEEE Transactions on Electron Devices, 60, 63–69.

    Article  Google Scholar 

  41. Sachid, A. B., Manoj, C. R., Sharma, D. K., & Rao, V. R. (2008). Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization. IEEE Electron Device Letters, 29, 128–130.

    Article  Google Scholar 

  42. Goel, A., Gupta, S., Bansal, A., Chiang, M.-H., & Roy, K. (2009). Double-gate MOSFETs with asymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM. In 2009 Device Res Conf., IEEE (pp. 57–58).

    Google Scholar 

  43. Sentaurus TCAD user’s manual. (2009). Synopsys Sentaurus Device (pp. 191–413). Retrieved from http://www.synopsys.com/

  44. Mohapatra, S. K., Pradhan, K. P., Singh, D., & Sahu, P. K. (2015). The role of geometry parameters and fin aspect ratio of sub-20nm SOI-FinFET: An analysis towards analog and RF circuit design. IEEE Transactions on Nanotechnology, 14, 546–554.

    Article  Google Scholar 

  45. Jain, N., & Raj, B. (2017). Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length. Journal of Semiconductors, 38, 122002.

    Article  Google Scholar 

  46. Jain, N., & Raj, B. (2018). Analysis and performance exploration of high performance (HfO2) SOI FinFETs over the conventional (Si3 N4) SOI FinFET towards analog/RF design. Journal of Semiconductors, 39, 124002.

    Article  Google Scholar 

  47. Pradhan, K. P., Mohapatra, S. K., Sahu, P. K., & Behera, D. K. (2014). Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectronics Journal, 45, 144–151.

    Article  Google Scholar 

  48. Ho, B., Sun, X., Shin, C., & Liu, T. J. K. (2013). Design optimization of multigate bulk MOSFETs. IEEE Transactions on Electron Devices, 60, 28–33.

    Article  Google Scholar 

  49. De Andrade, M. G. C., Martino, J. A., Aoulaiche, M., Collaert, N., Simoen, E., & Claeys, C. (2012). Behavior of triple-gate bulk FinFETs with and without DTMOS operation. Solid State Electronics, 71, 63–68.

    Article  Google Scholar 

  50. ITRS. (2013). International technology roadmap for semiconductors 2013; Executive summary. ITRS [internet], 80. Retrieved from http://www.itrs.net/ITRS

  51. Canali, C., Majni, G., Minder, R., & Ottaviani, G. (1975). Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature. IEEE Transactions on Electron Devices, 22, 1045–1047.

    Article  Google Scholar 

  52. Lombardi, C., Manzini, S., Saporito, A., & Vanzi, M. (1988). A physically based mobility model for numerical simulation of nonplanar devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 7, 1164–1171. Retrieved from http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=9186.

    Article  Google Scholar 

  53. Shockley, W., & Read, W. T. (1952). Statistics of the recombination of holes and electrons. Physics Review, 87, 835–842.

    Article  MATH  Google Scholar 

  54. Hall, R. N. (1952). Electron-hole recombination in germanium. Physics Review, 87, 387.

    Article  Google Scholar 

  55. Sze, S. M., & Ng, K. K. (2007). Physics of semiconductor devices (3rd ed., pp. 164, 682). New York: John Wiley Sons, Inc. Retrieved from http://www.wiley.com/WileyCDA/WileyTitle/productCd-0471143235.html

  56. Tan, T. H., & Goel, A. K. (2003). Zero-temperature-coefficient biasing point of a fully-depleted SOI MOSFET. Microwave and Optical Technology Letters, 37, 366–370.

    Article  Google Scholar 

  57. Groeseneken, G., Colinge, J. P., Maes, H. E., Alderman, J. C., & Holt, S. (1990). Temperature dependence of threshold voltage in thin-film SOI MOSFET’s. IEEE Electron Device Letters, 11, 329–331.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2020 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Jain, N., Raj, B. (2020). SOI FinFET for Computer Networks and Cyber Security Systems. In: Gupta, B., Perez, G., Agrawal, D., Gupta, D. (eds) Handbook of Computer Networks and Cyber Security. Springer, Cham. https://doi.org/10.1007/978-3-030-22277-2_12

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-22277-2_12

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-22276-5

  • Online ISBN: 978-3-030-22277-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics