Abstract
The key property of our design is resilience. So far we mostly covered system software methods and schemes to achieve or support it. Previous Chaps. 14 and 15 explained briefly what hardware (processor) should possess (including reduction on functions and limited in architecture options) to be able to implement resilience in the most efficient way. Here, we intend to analyze what we have achieved in hardware design in terms of malfunction tolerance—attempting to use heavy artillery of system software as less as possible, making dirty work of fault detection and determination (malfunction or permanent for hardware).
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Blaeser L, Monkman S, Schagaev I (2014) Evolving systems. In: Proceedings of the World Comp’14, USA, July 14. https://www.academia.edu/7685575/Evolving_systems_-_WorldComp_2014
Castano V, Schagaev I. Resilient computer system design. Springer. ISBN 978-3-319-15069-7
Intel Corporation (2009) Intel 64 and 32 architectures software developers manual, vol 1: basic architecture. Technical report 253665-032US
Intel Corporation (2004) Intel pxa255 processor developer’s manual. Technical report. Order number 278693-002, Intel Corporation, January 2004
ARM Limited (2005) ARM architecture reference manual. Technical report, ARM Limited
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Schagaev, I., Zouev, E., Thomas, K. (2020). ERRIC Reliability. In: Software Design for Resilient Computer Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-21244-5_16
Download citation
DOI: https://doi.org/10.1007/978-3-030-21244-5_16
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-21243-8
Online ISBN: 978-3-030-21244-5
eBook Packages: EngineeringEngineering (R0)