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Hardware Accelerators for Data Sort

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FPGA-BASED Hardware Accelerators

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 566))

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Abstract

This chapter is dedicated to sorting networks with regular and easily scalable structures, which permit data to be sorted and a number of supplementary problems to be solved. Two core architectures are discussed: (1) iterative that is based on a highly parallel combinational sorting network with minimal propagation delay, and (2) communication-time allowing data to be processed as soon as a new item is received and, thus, minimizing communication overhead that is frequently pointed out as the main bottleneck in system performance. The architectures are modeled in software (using Java language) and implemented in FPGA. It is shown that sorting is a base for many other data processing techniques, some of which have already been discussed in Chap. 3. Several new problems that are important for practical applications are highlighted, namely retrieving maximum and/or minimum sorted subsets, filtering (making it possible a set of data with the desired characteristics to be extracted), processing non-repeated items applying the address-based technique that has already been used in the previous chapter, traditional pipelining together with the introduced ring pipeline. The primary emphasis is on such important features as efficient pre-processing, uniformity of core components, rational combination of parallel, pipelined and sequential computations, and regularity of the circuits and interconnections. Potential alternative solutions are demonstrated and discussed. Many examples are given and analyzed with all necessary details.

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Author information

Authors and Affiliations

  1. Department of Electronics Telecommunications and Informatics, University of Aveiro, Aveiro, Portugal

    Iouliia Skliarova

  2. Department of Electronics Telecommunications and Informatics, University of Aveiro, Aveiro, Portugal

    Valery Sklyarov

Authors
  1. Iouliia Skliarova
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  2. Valery Sklyarov
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Correspondence to Iouliia Skliarova .

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Skliarova, I., Sklyarov, V. (2019). Hardware Accelerators for Data Sort. In: FPGA-BASED Hardware Accelerators. Lecture Notes in Electrical Engineering, vol 566. Springer, Cham. https://doi.org/10.1007/978-3-030-20721-2_4

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  • DOI: https://doi.org/10.1007/978-3-030-20721-2_4

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-20720-5

  • Online ISBN: 978-3-030-20721-2

  • eBook Packages: EngineeringEngineering (R0)

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