Abstract
This chapter is dedicated to searching networks, which permit to find extreme values in a set of data and to check if there are items satisfying some predefined conditions or limitations, indicated by given thresholds. The simplest task is retrieving the maximum and/or the minimum values. More complicated procedures permit the most frequent value/item to be found and a set of the most frequent values/items above a given threshold or satisfying some other constraint to be retrieved. The described above tasks may be solved for entire data sets, for intervals of data sets, or for specially organized structures, such as Boolean/ternary matrices. Different architectures are proposed that rely on: combinational and iterative searching networks, address-based technique, and some others. They are modelled in software (using Java language) and implemented in FPGA on the basis of the design technique described in the previous chapter. All necessary details for software and the basic VHDL modules for FPGA are presented and discussed. Searching maximum/minimum items in very large data sets and pipelining are also overviewed. The networks of this chapter will be used as components of more complicated systems considered in subsequent chapters.
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Skliarova, I., Sklyarov, V. (2019). Hardware Accelerators for Data Search. In: FPGA-BASED Hardware Accelerators. Lecture Notes in Electrical Engineering, vol 566. Springer, Cham. https://doi.org/10.1007/978-3-030-20721-2_3
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DOI: https://doi.org/10.1007/978-3-030-20721-2_3
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