Abstract
Manufacturing processes of modern ultra-large-scale integrated circuits are highly complex and costly. Defects generated in the manufacturing processes are unavoidable and affect not only manufacturing yield but also device reliability. In this reason, accurate modeling of the spatial defects distribution is imperatively important for yield and reliability estimation as well as process improvement. Defects on semiconductor wafers tend to cluster, which introduces excessive zeros, causing over-dispersion in defect count data. This chapter discusses some latest development in modeling the non-homogeneously distributed spatial defect counts, focusing on Bayesian spatial regression approaches based on Poisson models, negative binomial models, and zero-inflated models. Real wafer map data are used to evaluate the performance of these models. In addition, the yield models are extended to build extrinsic reliability models based on a defect-growth concept.
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Acknowledgements
This work is partially supported by the National Science Foundation projects 1633500 and 1633580. The work of S. J. Bae was supported by the Technological Innovation R&D Program (S2480669) funded by the Small and Medium Business Administration(SMBA), Korea.
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Yuan, T., Bae, S.J., Kuo, Y. (2019). Defects Driven Yield and Reliability Modeling for Semiconductor Manufacturing. In: Lio, Y., Ng, H., Tsai, TR., Chen, DG. (eds) Statistical Quality Technologies. ICSA Book Series in Statistics. Springer, Cham. https://doi.org/10.1007/978-3-030-20709-0_16
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