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Introduction to Wearout

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Abstract

Over the last decade, CMOS wearout emerged as one of the most critical threats to circuit performance and system reliability. Among recognized wearout mechanisms, bias temperature instability (BTI) and electromigration (EM) appear as two dominant effects that affect transistors and interconnect, respectively. Conventional flat guardband or dynamic margin design approaches address these effects by tolerating them, but they can be both costly and insufficient. Techniques that can take advantage of recovery of the phenomena can be more economic and effective. In this chapter, we present a taxonomy of state-of-the-art BTI and EM mitigation techniques that were developed across the system hierarchy, followed by the introduction of the concept of accelerated active self-healing that will be addressed throughout the rest of the book.

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Notes

  1. 1.

    In this book, the terms “aging” and “wearout” are used interchangeably. Circuit aging/wearout refers to wearout effects at both transistor level and interconnect level. Transistor aging/wearout mainly refers to BTI effect or other effects that affect CMOS transistors.

  2. 2.

    In this book, terms “accelerated active self-healing” and “accelerated and active recovery” are used interchangeably.

References

  1. Muhammad Shafique, Siddharth Garg, Jörg Henkel, and Diana Marculescu. The eda challenges in the dark silicon era: Temperature, reliability, and variability perspectives. In Proceedings of the 51st Annual Design Automation Conference, pages 1–6. ACM, 2014.

    Google Scholar 

  2. Jeonghee Shin, Victor Zyuban, Pradip Bose, and Timothy M Pinkston. A proactive wearout recovery approach for exploiting microarchitectural redundancy to extend cache sram lifetime. In ACM SIGARCH Computer Architecture News, volume 36, pages 353–362. IEEE Computer Society, 2008.

    Google Scholar 

  3. Robert Baumann. Soft errors in advanced computer systems. IEEE Design & Test of Computers, 22(3):258–266, 2005.

    Article  Google Scholar 

  4. ITRS Report. http://www.itrs2.net/itrs-reports.html.

  5. James H Stathis, M Wang, RG Southwick, EY Wu, BP Linder, EG Liniger, G Bonilla, and H Kothari. Reliability challenges for the 10nm node and beyond. In Electron Devices Meeting (IEDM), 2014 IEEE International, pages 20–6. IEEE, 2014.

    Google Scholar 

  6. Rob Aitken, Ethan H Cannon, Mondira Pant, and Mehdi B Tahoori. Resiliency challenges in sub-10nm technologies. In VLSI Test Symposium (VTS), 2015 IEEE 33rd, pages 1–4. IEEE, 2015.

    Google Scholar 

  7. Fabian Oboril and Mehdi B Tahoori. Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist. In Test Conference (ITC), 2015 IEEE International, pages 1–10. IEEE, 2015.

    Google Scholar 

  8. Shekhar Borkar. Private communication, 2018.

    Google Scholar 

  9. SM Ramey, C Prasad, and A Rahman. Technology scaling implications for BTI reliability. Microelectronics Reliability, 82:42–50, 2018.

    Article  Google Scholar 

  10. Souvik Mahapatra. Fundamentals of Bias Temperature Instability in MOS Transistors. Springer, 2016.

    Book  Google Scholar 

  11. Jacopo Franco, Salvatore Graziano, Ben Kaczer, Felice Crupi, L-Å Ragnarsson, Tibor Grasser, and Guido Groeseneken. Bti reliability of ultra-thin eot mosfets for sub-threshold logic. Microelectronics Reliability, 52(9):1932–1935, 2012.

    Article  Google Scholar 

  12. Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, and Michael Fritze. Cross-layer modeling and simulation of circuit reliability. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 33(1):8–23, 2014.

    Google Scholar 

  13. Xin Huang, Valeriy Sukharev, Taeyoung Kim, and Sheldon X-D Tan. Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing. Integration, the VLSI Journal, 2016.

    Google Scholar 

  14. C Prasad, S Ramey, and L Jiang. Self-heating in advanced cmos technologies. In Reliability Physics Symposium (IRPS), 2017 IEEE International, pages 6A–4. IEEE, 2017.

    Google Scholar 

  15. Brian Bailey. Chip aging becomes design problem. Semiconductor Engineering, 2018.

    Google Scholar 

  16. Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma Vrudhula, Frank Liu, and Yu Cao. The impact of nbti on the performance of combinational and sequential circuits. In Proceedings of the 44th annual Design Automation Conference, pages 364–369. ACM, 2007.

    Google Scholar 

  17. Weisong Shi and Schahram Dustdar. The promise of edge computing. Computer, 49(5):78–81, 2016.

    Article  Google Scholar 

  18. Jan M Rabaey, Anantha P Chandrakasan, and Borivoje Nikolic. Digital integrated circuits, volume 2. Prentice hall Englewood Cliffs, 2002.

    Google Scholar 

  19. Ed Sperling. Chip Aging Accelerates. Semiconductor Engineering, 2018.

    Google Scholar 

  20. Massimo Alioto. Enabling the Internet of Things: From Integrated Circuits to Integrated Systems. Springer, 2017.

    Book  Google Scholar 

  21. Jörg Henkel, Lars Bauer, Nikil Dutt, Puneet Gupta, Sani Nassif, Muhammad Shafique, Mehdi Tahoori, and Norbert Wehn. Reliable on-chip systems in the nano-era: lessons learnt and future trends. In Proceedings of the 50th Annual Design Automation Conference, page 99. ACM, 2013.

    Google Scholar 

  22. Bipul C Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Alam, Kaushik Roy, et al. Impact of nbti on the temporal performance degradation of digital circuits. Electron Device Letters, IEEE, 26(8):560–562, 2005.

    Google Scholar 

  23. Hyejeong Hong, Jaeil Lim, Hyunyul Lim, and Sungho Kang. Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability. ACM Computing Surveys (CSUR), 48(1):9, 2015.

    Google Scholar 

  24. Runsheng Wang, Pengpeng Ren, Changze Liu, Shaofeng Guo, and Ru Huang. Understanding nbti-induced dynamic variability in the nano-reliability era: From devices to circuits. In Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the, pages 119–121. IEEE, 2015.

    Google Scholar 

  25. Kerry Bernstein, David J Frank, Anne E Gattiker, Wilfried Haensch, Brian L Ji, Sani R Nassif, Edward J Nowak, Dale J Pearson, and Norman J Rohrer. High-performance cmos variability in the 65-nm regime and beyond. IBM journal of research and development, 50(4.5):433–449, 2006.

    Article  Google Scholar 

  26. Sheldon X-D Tan, Hussam Amrouch, Taeyoung Kim, Zeyu Sun, Chase Cook, and Jörg Henkel. Recent advances in em and bti induced reliability modeling, analysis and optimization. Integration, the VLSI Journal, 2017.

    Google Scholar 

  27. D. C. Sekar et al. Electromigration Resistant Power Delivery Systems. IEEE Electron Device Letters, 28(8):767–769, Aug 2007.

    Article  Google Scholar 

  28. Navid Khoshavi, Rizwan A Ashraf, Ronald F DeMara, Saman Kiamehr, Fabian Oboril, and Mehdi B Tahoori. Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods. Integration, the VLSI Journal, 59:10–22, 2017.

    Article  Google Scholar 

  29. Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, and Kaushik Roy. NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? In Proceedings of the 2008 Asia and South Pacific Design Automation Conference, pages 726–731. IEEE Computer Society Press, 2008.

    Google Scholar 

  30. Lide Zhang and Robert P Dick. Scheduled voltage scaling for increasing lifetime in the presence of nbti. In Proceedings of the Asia and South Pacific Design Automation Conference, pages 492–497. IEEE Press, 2009.

    Google Scholar 

  31. Saman Kiamehr, Farshad Firouzi, Mojtaba Ebrahimi, and Mehdi B Tahoori. Aging-aware standard cell library design. In Proceedings of the conference on Design, Automation & Test in Europe, page 261. European Design and Automation Association, 2014.

    Google Scholar 

  32. Rizwan A Ashraf, Navid Khoshavi, Ahmad Alzahrani, Ronald F DeMara, Saman Kiamehr, and Mehdi B Tahoori. Area-energy tradeoffs of logic wear-leveling for bti-induced aging. In Proceedings of the ACM International Conference on Computing Frontiers, pages 37–44. ACM, 2016.

    Google Scholar 

  33. Jayanth Srinivasan, Sarita V Adve, Pradip Bose, and Jude A Rivers. Exploiting structural duplication for lifetime reliability enhancement. In Computer Architecture, 2005. ISCA’05. Proceedings. 32nd International Symposium on, pages 520–531. IEEE, 2005.

    Google Scholar 

  34. Navid Khoshavi, Rizwan A Ashraf, and Ronald F DeMara. Applicability of power-gating strategies for aging mitigation of CMOS logic paths. In Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on, pages 929–932. IEEE, 2014.

    Google Scholar 

  35. S Sarma, N Dutt, N Venkatasubramanian, A Nicolau, and P Gupta. Cyberphysical system-on-chip (cpsoc): Sensor actuator rich self-aware computational platform. University of California Irvine, Tech. Rep. CECS TR-13-06, 2013.

    Google Scholar 

  36. Kai He, Xin Huang, and Sheldon X-D Tan. Em-based on-chip aging sensor for detection and prevention of counterfeit and recycled ics. In Computer-Aided Design (ICCAD), 2015 IEEE/ACM International Conference on, pages 146–151. IEEE, 2015.

    Google Scholar 

  37. Fabian Oboril and Mehdi B Tahoori. Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation. In Test Symposium (ETS), 2012 17th IEEE European, pages 1–6. IEEE, 2012.

    Google Scholar 

  38. Zhenyu Qi and Mircea R Stan. Nbti resilient circuits using adaptive body biasing. In Proceedings of the 18th ACM Great Lakes symposium on VLSI, pages 285–290. ACM, 2008.

    Google Scholar 

  39. Evelyn Mintarno et al. Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging. IEEE TCAD, 30(5):760–773, 2011.

    Google Scholar 

  40. Taniya Siddiqua and Sudhanva Gurumurthi. Nbti-aware dynamic instruction scheduling. In Proceedings of the 5th Workshop on Silicon Errors in Logic-System Effects. Citeseer, 2009.

    Google Scholar 

  41. Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, and Yu Cao. Physics matters: statistical aging prediction under trapping/detrapping. In Proceedings of the 49th Annual Design Automation Conference, pages 139–144. ACM, 2012.

    Google Scholar 

  42. Saket Gupta and Sachin S Sapatnekar. Employing circadian rhythms to enhance power and reliability. ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(3):38, 2013.

    Article  Google Scholar 

  43. Xinfei Guo. Towards Wearout-Aware and Accelerated Self-Healing Digital Systems. PhD Thesis, University of Virginia, 2018.

    Google Scholar 

  44. Xinfei Guo, Wayne Burleson, and Mircea Stan. Modeling and experimental demonstration of accelerated self-healing techniques. In Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE, pages 1–6. IEEE, 2014.

    Google Scholar 

  45. Xinfei Guo and Mircea R Stan. Work hard, sleep well-avoid irreversible ic wearout with proactive rejuvenation. In Design Automation Conference (ASP-DAC), 2016 21st Asia and South Pacific, pages 649–654. IEEE, 2016.

    Google Scholar 

  46. Xinfei Guo and Mircea R Stan. Enabling Wearout-Immune BEOL and FEOL with Active Rejuvenation. In IEEE/ACM Workshop on Variability Modeling and Characterization (VMC), 2017.

    Google Scholar 

  47. Xinfei Guo and Mircea R Stan. MCPENS: Multiple-Critical-Path Embeddable NBTI Sensors for Dynamic Wearout Management. In Workshop on Silicon Errors in Logic-System Effects (SELSE-11). IEEE, 2015.

    Google Scholar 

  48. Xinfei Guo and Mircea R Stan. Implications of accelerated self-healing as a key design knob for cross-layer resilience. Integration, the VLSI Journal, 56:167–180, 2017.

    Article  Google Scholar 

  49. Xinfei Guo and Mircea R Stan. Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery. In Dependable Systems and Networks Workshop (DSN-W), 2017 47th Annual IEEE/IFIP International Conference on, pages 184–191. IEEE, 2017.

    Google Scholar 

  50. Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, and Mircea R Stan. Back to the Future: Digital Circuit Design in the FinFET Era. Journal of Low Power Electronics, 13(3):338–355, 2017.

    Article  Google Scholar 

  51. Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, and Mircea R Stan. When “things” get older - Exploring Circuit Aging in IoT Applications. In Quality Electronic Design (ISQED), International Symposium on. IEEE, 2018.

    Google Scholar 

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Guo, X., Stan, M.R. (2020). Introduction to Wearout. In: Circadian Rhythms for Future Resilient Electronic Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-20051-0_1

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  • DOI: https://doi.org/10.1007/978-3-030-20051-0_1

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