Leros: The Return of the Accumulator Machine

  • Martin SchoeberlEmail author
  • Morten Borup Petersen
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11479)


An accumulator instruction set architecture is simpler than an instruction set of a (reduced instruction set computer) RISC architecture. Therefore, an accumulator instruction set that does within one instruction less than a typical RISC instruction is probably more “reduced” than a standard load/store register based RISC architecture.

This paper presents Leros, an accumulator machine and its supporting C compiler. The hypothesis of the Leros instruction set architecture is that it can deliver the same performance as a RISC pipeline, but consumes less hardware and therefore also less power.


Embedded systems Minimal processor 


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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  1. 1.Department of Applied Mathematics and Computer ScienceTechnical University of DenmarkKongens LyngbyDenmark

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