Abstract
Multi-core processors, despite their technical and economic advantages, are yet hesitantly adopted in safety-critical embedded application domains such as automotive and avionics. A key issue is the potential interference on shared resources, such as interconnect and memory, between applications of different criticality which are running on a Multi-Processor System-on-Chip (MPSoC) with tens of individual cores. In this paper we propose the introduction of established protection switching, known from synchronous data networks, to a hybrid Network-on-Chip (NoC) in order to provide fault-tolerance for critical connections. Our hybrid NoC combines configurable Time-Division-Multiplexing (TDM) for critical task traffic with conventional packet switching for Best-Effort (BE) traffic. We analyze three different protection switching schemes for their worst case latencies in case of faulty NoC links and their resource overheads. Simulations with random traffic and 10% reserved resources for TDM connections reveal that the degradation of BE traffic performance due to the proposed TDM protection switching for critical traffic remains limited to about a 5% lower injection rate even in case of 1+1 protection, which can hence be considered affordable. We conclude that the proposed hybrid NoC is a suitable way to provide both hard real-time guarantees and fault-tolerance for critical connections in advanced MPSoCs.
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The work presented in this paper is supported by the German BMBF project ARAMiS II with funding ID 01 IS 16025.
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Koenen, M., Doan, N.A.V., Wild, T., Herkersdorf, A. (2019). A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_3
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DOI: https://doi.org/10.1007/978-3-030-18656-2_3
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