Abstract
Multi and many-core SoCs (System-on-Chip) are the key solutions to cater for extraordinary demands of high-performance embedded and other applications. It has become more critical with the limits on sub-nanometer technologies for chips that cannot be shrunk further. Network on Chip (NoC) is a scalable interconnection structure that can provide efficient solutions for on-chip interconnection problems of many-core SoCs such as re-configurability for application specific applications. Most of the existing reconfigurable NoCs improve performance of SoC in exchange of larger chip area and higher power. We present a new reconfigurable NoC having improved performance and power for variety of SoC applications. The synthesis and simulation results for our approach show higher performance by comparing our NoC architecture with the past on-chip interconnection structures.
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The authors acknowledge the financial support from Ryerson University and Computing System support from CMC microsystems.
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Khan, G.N., Gharan, M.O. (2019). Application Specific Reconfigurable SoC Interconnection Network Architecture. In: Schoeberl, M., Hochberger, C., Uhrig, S., Brehm, J., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2019. ARCS 2019. Lecture Notes in Computer Science(), vol 11479. Springer, Cham. https://doi.org/10.1007/978-3-030-18656-2_24
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DOI: https://doi.org/10.1007/978-3-030-18656-2_24
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