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A Minimal Network Interface for a Simple Network-on-Chip

  • Martin SchoeberlEmail author
  • Luca Pezzarossa
  • Jens Sparsø
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11479)

Abstract

Network-on-chip implementations are typically complex in the design of the routers and the network interfaces. The resource consumption of such routers and network interfaces approaches the size of an in-order processor pipeline. For the job of just moving data between processors, this may be considered too much overhead. This paper presents a lightweight network-on-chip solution. We build on the S4NOC for the router design and add a minimal network interface. The presented architecture supports the transfer of single words between all processor cores. Furthermore, as we use time-division multiplexing of the router and link resources, the latency of such transfers is upper bounded. Therefore, this network-on-chip can be used for real-time systems. The router and network interface together consume around 6% of the resources of a RISC processor pipeline.

Keywords

Network-on-chip Network interface Real-time systems Multicore processor Communication 

Notes

Acknowledgment

We would like to thank Constantina Ioannou for bringing up the idea of simply using a FIFO as a network interface.

The work presented in this paper was partially funded by the Danish Council for Independent Research | Technology and Production Sciences under the project PREDICT (http://predict.compute.dtu.dk/), contract no. 4184-00127A.

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Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Martin Schoeberl
    • 1
    Email author
  • Luca Pezzarossa
    • 1
  • Jens Sparsø
    • 1
  1. 1.Department of Applied Mathematics and Computer ScienceTechnical University of DenmarkKongens LyngbyDenmark

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