A Generic Functional Simulation of Heterogeneous Systems

  • Sebastian RachujEmail author
  • Marc Reichenbach
  • Dietmar Fey
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 11479)


Virtual Prototypes are often used for software development before the actual hardware configuration of the finished product is available. Today’s platforms often provide different kinds of processors forming a heterogeneous system. For example, ADAS applications require dedicated realtime processors, parallel accelerators like graphics cards and general purpose CPUs. This paper presents an approach for creating a simulation system for a heterogeneous system by using already available processor models. The approach is intended to be flexible and to support different kinds of models to fulfill the requirements of a heterogeneous system. Simulators should easily be exchangeable by simulators with the same architecture support. It was possible to identify the SystemC connection of the considered general purpose CPU models as a bottleneck for the simulation speed. The connection to the realtime core suffers from a necessary connection via the network which is evaluated in more detail. Combining the GPU emulator with the rest of the system reduces the simulation speed of the CUDA kernels in a negligible manner.


  1. 1.
    Aaamodt, T., Boktor, A.: GPGPU-Sim 3.x: a performance simulator for many-core accelerator research. In: International Symposium on Computer Architecture (ISCA) (2012).
  2. 2.
    Anwar Taie, M.: New trends in automotive software design for the challenges of active safety and autonomous vehicles. In: FAST-zero’15: 3rd International Symposium on Future Active Safety Technology Toward Zero Traffic Accidents 2015 (2015)Google Scholar
  3. 3.
    Binkert, N., et al.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011)CrossRefGoogle Scholar
  4. 4.
    Black, F., Scholes, M.: The pricing of options and corporate liabilities. J. Polit. Econ. 81(3), 637–654 (1973)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Delicia, G.S.P., Bruckschloegl, T., Figuli, P., Tradowsky, C., Almeida, G.M., Becker, J.: Bringing accuracy to open virtual platforms (OVP): a safari from high-level tools to low-level microarchitectures. In: IJCA Proceedings on International Conference on Innovations in Intelligent Instrumentation, Optimization and Electrical Sciences ICIIIOES, no. 10, pp. 22–27. Citeseer (2013)Google Scholar
  6. 6.
    Diamos, G.F., Kerr, A.R., Yalamanchili, S., Clark, N.: Ocelot: a dynamic optimization framework for bulk-synchronous applications in heterogeneous systems. In: Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, pp. 353–364. ACM, New York (2010)Google Scholar
  7. 7.
    Dikmen, M., Burns, C.: Trust in autonomous vehicles: the case of tesla autopilot and summon. In: 2017 IEEE International Conference on Systems, Man, and Cybernetics (SMC), pp. 1093–1098, October 2017Google Scholar
  8. 8.
    Greenblatt, N.A.: Self-driving cars and the law. IEEE Spectr. 53(2), 46–51 (2016)MathSciNetCrossRefGoogle Scholar
  9. 9.
    Gutierrez, A., et al.: Lost in abstraction: pitfalls of analyzing GPUs at the intermediate language level. In: 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 608–619, February 2018Google Scholar
  10. 10.
    IEEE Computer Society: IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std 1666–2011 (2012)Google Scholar
  11. 11.
    Leupers, R., et al.: Virtual platforms: breaking new grounds. In: 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 685–690, March 2012Google Scholar
  12. 12.
    Menard, C., Jung, M., Castrillon, J., Wehn, N.: System simulation with gem5 and Systemc: the keystone for full interoperability. In: Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS). IEEE, July 2017Google Scholar
  13. 13.
    Power, J., Hestness, J., Orr, M.S., Hill, M.D., Wood, D.A.: gem5-gpu: a heterogeneous CPU-GPU simulator. IEEE Comput. Archit. Lett. 14(1), 34–36 (2015)CrossRefGoogle Scholar
  14. 14.
    Reichenbach, M., Liebischer, L., Vaas, S., Fey, D.: Comparison of lane detection algorithms for ADAS using embedded hardware architectures. In: 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 48–53, October 2018Google Scholar
  15. 15.
    Schoenwetter, D., Ditter, A., Aizinger, V., Reuter, B., Fey, D.: Cache aware instruction accurate simulation of a 3-D coastal ocean model on low power hardware. In: 2016 6th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH), pp. 1–9, July 2016Google Scholar
  16. 16.
    Skende, A.: Introducing “parker”: next-generation tegra system-on-chip. In: 2016 IEEE Hot Chips 28 Symposium (HCS), August 2016Google Scholar
  17. 17.
    Ubal, R., Jang, B., Mistry, P., Schaa, D., Kaeli, D.: Multi2Sim: a simulation framework for CPU-GPU computing. In: 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 335–344, September 2012Google Scholar
  18. 18.
    Weinstock, J.H., Leupers, R., Ascheid, G., Petras, D., Hoffmann, A.: Systemc-link: parallel systemc simulation using time-decoupled segments. In: 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 493–498, March 2016Google Scholar

Copyright information

© Springer Nature Switzerland AG 2019

Authors and Affiliations

  • Sebastian Rachuj
    • 1
    Email author
  • Marc Reichenbach
    • 1
  • Dietmar Fey
    • 1
  1. 1.Friedrich-Alexander University Erlangen-Nürnberg (FAU)ErlangenGermany

Personalised recommendations